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W956A8MBYA Datasheet Preview

W956A8MBYA Datasheet

64Mb HyperRAM

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W956D8MBYA / W956A8MBYA
64Mb HyperRAM
Table of Contents-
1. FEATURES.................................................................................................................................................................................. 3
2. ORDER INFORMATION .............................................................................................................................................................. 3
3. BALL ASSIGNMENT.................................................................................................................................................................... 4
4. BALL DESCRIPTIONS ................................................................................................................................................................ 5
5. BLOCK DIAGRAM ....................................................................................................................................................................... 6
6. FUNCTIONAL DESCRIPTION..................................................................................................................................................... 7
6.1 HyperBus Interface ........................................................................................................................................................ 7
7. HYPERBUS TRANSACTION DETAILS..................................................................................................................................... 10
7.1 Command/Address Bit Assignments............................................................................................................................ 10
7.2 Read Transactions....................................................................................................................................................... 13
7.3 Write Transactions (Memory Array Write).................................................................................................................... 15
7.4 Write Transactions without Initial Latency (Register Write) .......................................................................................... 17
8. MEMORY SPACE...................................................................................................................................................................... 18
8.1 HyperBus Interface Memory Space addressing........................................................................................................... 18
8.1.1 Density and Row Boundaries......................................................................................................................... 18
9. REGISTER SPACE ................................................................................................................................................................... 19
9.1 HyperBus Interface Register Addressing ..................................................................................................................... 19
9.2 Register Space Access................................................................................................................................................ 21
9.3 Device Identification Registers..................................................................................................................................... 22
9.4 Configuration Register 0 .............................................................................................................................................. 22
9.4.1 Wrapped Burst ............................................................................................................................................... 23
9.4.2 Hybrid Burst ................................................................................................................................................... 24
9.4.3 Initial Latency................................................................................................................................................. 25
9.4.4 Fixed Latency ................................................................................................................................................ 25
9.4.5 Drive Strength ................................................................................................................................................ 25
9.4.6 Deep Power Down ......................................................................................................................................... 25
9.5 Configuration Register 1 .............................................................................................................................................. 26
9.5.1 Master Clock Type ......................................................................................................................................... 26
9.5.2 Partial Array Refresh...................................................................................................................................... 26
9.5.3 Hybrid Sleep .................................................................................................................................................. 27
9.5.4 Distributed Refresh Interval ........................................................................................................................... 27
10. INTERFACE STATES................................................................................................................................................................ 28
10.1 IO condition of interface states..................................................................................................................................... 28
10.2 Power Conservation Modes ......................................................................................................................................... 29
10.2.1 Interface Standby........................................................................................................................................... 29
10.2.2 Active Clock Stop........................................................................................................................................... 29
10.2.3 Hybrid Sleep .................................................................................................................................................. 29
10.2.4 Deep Power Down ......................................................................................................................................... 30
11. ELECTRICAL SPECIFICATIONS .............................................................................................................................................. 31
11.1 Absolute Maximum Ratings ......................................................................................................................................... 31
11.2 Latch up Characteristics .............................................................................................................................................. 31
11.3 Operating Ranges........................................................................................................................................................ 31
11.3.1 DC Characteristics ......................................................................................................................................... 31
11.3.2 Operating Temperature.................................................................................................................................. 31
The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or
reproduced without permission from Winbond.
Publication Release Date: Sep. 25, 2019
Revision: A01-001
-1-




Winbond

W956A8MBYA Datasheet Preview

W956A8MBYA Datasheet

64Mb HyperRAM

No Preview Available !

W956D8MBYA / W956A8MBYA
11.3.3 ICC Characteristics ........................................................................................................................................ 32
11.3.4 Power-Up Initialization ................................................................................................................................... 33
11.3.5 Power-Down .................................................................................................................................................. 35
11.3.6 Hardware Reset ............................................................................................................................................. 36
11.3.7 Capacitance Characteristics .......................................................................................................................... 37
11.4 Input Signal Overshoot ................................................................................................................................................ 37
12. TIMING SPECIFICATIONS........................................................................................................................................................ 38
12.1 Key to Switching Waveforms ....................................................................................................................................... 38
12.2 AC Test Conditions ...................................................................................................................................................... 38
12.3 AC Characteristics ....................................................................................................................................................... 39
12.3.1 Read Transactions......................................................................................................................................... 39
12.3.2 Write Transactions ......................................................................................................................................... 42
12.3.3 Hybrid Sleep Timings..................................................................................................................................... 44
12.3.4 Deep Power down Timings ............................................................................................................................ 44
13. PACKAGE SPECIFICATION ..................................................................................................................................................... 45
14. REVISION HISTORY ................................................................................................................................................................. 46
The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or
reproduced without permission from Winbond.
Publication Release Date: Sep. 25, 2019
Revision: A01-001
-2-


Part Number W956A8MBYA
Description 64Mb HyperRAM
Maker Winbond
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