1. GENERAL DESCRIPTION
64Mb Async./Burst/Sync./A/D MUX
Winbond x16 ADMUX products are high-speed, CMOS pseudo-static random access memory developed for low-
power, portable applications. The device has a DRAM core organized. These devices are a variation of the industry-
standard Flash control interface, with a multiplexed address/data bus. The multiplexed address and data functionality
dramatically reduce the required signal count, and increase READ/WRITE bandwidth.
For seamless operation on a burst Flash bus, Winbond x16 ADMUX products incorporate a transparent self-refresh
mechanism. The hidden refresh requires no additional support from the system memory controller and has no
significant impact on device READ/WRITE performance.
Two user-accessible control registers define device operation. The bus configuration register (BCR) defines how the
Winbond x16 ADMUX device interacts with the system memory bus and is nearly identical to its counterpart on burst
mode Flash devices. The refresh configuration register (RCR) is used to control how refresh is performed on the
DRAM array. These registers are automatically loaded with default settings during power-up and can be updated
anytime during normal operation.
Special attention has been focused on standby current consumption during self refresh. Winbond x16 ADMUX
products include two mechanisms to minimize standby current. Partial-array refresh (PAR) enables the system to limit
refresh to only that part of the DRAM array that contains essential data. Temperature-compensated refresh (TCR)
uses an on-chip sensor to adjust the refresh rate to match the device temperature—the refresh rate decreases at
lower temperatures to minimize current consumption during standby. The system-configurable refresh mechanisms
are accessed through the RCR.
Winbond x16 ADMUX is compliant with the industry-standard CellularRAM 1.5 x16 A/D MUX.
•Supports asynchronous and burst operations
• VCC, VCCQ Voltages:
• Random access time: 70ns
• Burst mode READ and WRITE access:
4, 8, 16, or 32 words, or continuous burst
Burst wrap or sequential
Max clock rate: 133 MHz (tCLK = 7.5ns)
• Low power consumption:
Asynchronous READ: <25 mA
Continuous burst READ: <35 mA
Standby current: 250μA
On-chip temperature compensated refresh (TCR)
Partial array refresh (PAR)
Deep power-down (DPD) mode
Package: 54 Ball VFBGA
16-bit multiplexed address/data bus
Operating temperature range: -40°C~85°C
Publication Release Date : May 29,2013
- 1 - Revision : A01-003