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XC95108 Datasheet Preview

XC95108 Datasheet

XC95108 In-System Programmable CPLD

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– PRODUCT OBSOLETE / UNDER OBSOLESCENCE –
0
R XC95108 In-System
Programmable CPLD
DS066 (v5.0) May 17, 2013
05
Features
• 7.5 ns pin-to-pin logic delays on all pins
• fCNT to 125 MHz
• 108 macrocells with 2,400 usable gates
• Up to 108 user I/O pins
• 5V in-system programmable
- Endurance of 10,000 program/erase cycles
- Program/erase over full commercial voltage and
temperature range
• Enhanced pin-locking architecture
• Flexible 36V18 Function Block
- 90 product terms drive any or all of 18 macrocells
within Function Block
- Global and product term clocks, output enables,
set and reset signals
• Extensive IEEE Std 1149.1 boundary-scan (JTAG)
support
• Programmable power reduction mode in each
macrocell
• Slew rate control on individual outputs
• User programmable ground pin capability
• Extended pattern security features for design
protection
• High-drive 24 mA outputs
• 3.3V or 5V I/O capability
• Advanced CMOS 5V FastFLASH™ technology
• Supports parallel programming of more than one
XC9500 concurrently
• Available in 84-pin PLCC, 100-pin PQFP, 100-pin
TQFP, and 160-pin PQFP packages
Product Specification
Description
The XC95108 is a high-performance CPLD providing
advanced in-system programming and test capabilities for
general purpose logic integration. It is comprised of eight
36V18 Function Blocks, providing 2,400 usable gates with
propagation delays of 7.5 ns. See Figure 2 for the architec-
ture overview.
Power Management
Power dissipation can be reduced in the XC95108 by con-
figuring macrocells to standard or low-power modes of
operation. Unused macrocells are turned off to minimize
power dissipation.
Operating current for each design can be approximated for
specific operating conditions using the following equation:
ICC (mA) = MCHP (1.7) + MCLP (0.9) + MC (0.006 mA/MHz) f
Where:
MCHP = Macrocells in high-performance mode
MCLP = Macrocells in low-power mode
MC = Total number of macrocells used
f = Clock frequency (MHz)
Figure 1 shows a typical calculation for the XC95108
device.
300
200
(180)
100
High Performance
Low Power
(250)
(170)
0 50 100
Clock Frequency (MHz)
DS066_01_110501
Figure 1: Typical ICC vs. Frequency for XC95108
© 1998, 2003–2006, 2013 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS066 (v5.0) May 17, 2013
Product Specification
www.xilinx.com
1




Xilinx

XC95108 Datasheet Preview

XC95108 Datasheet

XC95108 In-System Programmable CPLD

No Preview Available !

– PRODUCT OBSOLETE / UNDER OBSOLESCENCE –
XC95108 In-System Programmable CPLD
JTAG Port
3
1
JTAG
Controller
In-System Programming Controller
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O/GCK
I/O/GSR
I/O/GTS
3
1
2
I/O
Blocks
36
18
36
18
36
18
36
18
36
18
36
18
Function
Block 1
Macrocells
1 to 18
Function
Block 2
Macrocells
1 to 18
Function
Block 3
Macrocells
1 to 18
Function
Block 4
Macrocells
1 to 18
Function
Block 5
Macrocells
1 to 18
Function
Block 6
Macrocells
1 to 18
R
Figure 2: XC95108 Architecture
Function block outputs (indicated by the bold line) drive the I/O blocks directly.
DS066_02_110101
2
www.xilinx.com
DS066 (v5.0) May 17, 2013
Product Specification


Part Number XC95108
Description XC95108 In-System Programmable CPLD
Maker Xilinx
Total Page 10 Pages
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