Datasheet Summary
®
XC95108 In-System Programmable CPLD
1 1-
December 4, 1998 (Version 3.0)
Product Specification
Features
- -
- -
- 7.5 ns pin-to-pin logic delays on all pins fCNT to 125 MHz 108 macrocells with 2400 usable gates Up to 108 user I/O pins 5 V in-system programmable (ISP)
- Endurance of 10,000 program/erase cycles
- Program/erase over full mercial voltage and temperature range Enhanced pin-locking architecture Flexible 36V18 Function Block
- 90 product terms drive any or all of 18 macrocells within Function Block
- Global and product term clocks, output enables, set and reset signals Extensive IEEE Std 1149.1 boundary-scan (JTAG) support Programmable power reduction mode in each...