* 7.5 ns pin-to-pin logic delays on all pins fCNT to 111 MHz 144 macrocells with 3,200 usable gates Up to 133 user I/O pins 5 V in-system programmable - Endurance of 10,000 program/erase cycles - Program/erase over full commercial voltage and temperatu
XC95144
Xilinx
74.54 KB
Xc95144 in-system programmable cpld.
1 ® XC95144 In-System Programmable CPLD 1 1 December 4, 1998 (Version 4.0) Product Specification Operating current for each design can be app.
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