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XC95144 Datasheet Preview

XC95144 Datasheet

XC95144 In-System Programmable CPLD

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1
® XC95144 In-System Programmable
CPLD
December 4, 1998 (Version 4.0)
1 1* Product Specification
Features
• 7.5 ns pin-to-pin logic delays on all pins
• fCNT to 111 MHz
• 144 macrocells with 3,200 usable gates
• Up to 133 user I/O pins
• 5 V in-system programmable
- Endurance of 10,000 program/erase cycles
- Program/erase over full commercial voltage and
temperature range
• Enhanced pin-locking architecture
• Flexible 36V18 Function Block
- 90 product terms drive any or all of 18 macrocells
within Function Block
- Global and product term clocks, output enables, set
and reset signals
• Extensive IEEE Std 1149.1 boundary-scan (JTAG)
support
• Programmable power reduction mode in each
macrocell
• Slew rate control on individual outputs
• User programmable ground pin capability
• Extended pattern security features for design protection
• High-drive 24 mA outputs
• 3.3 V or 5 V I/O capability
• Advanced CMOS 5V FastFLASH technology
• Supports parallel programming of more than one
XC9500 concurrently
• Available in 100-pin PQFP, 100-pin TQFP, and 160-pin
PQFP packages
Description
The XC95144 is a high-performance CPLD providing
advanced in-system programming and test capabilities for
general purpose logic integration. It is comprised of eight
36V18 Function Blocks, providing 3,200 usable gates with
propagation delays of 7.5 ns. See Figure 2 for the architec-
ture overview.
Power Management
Power dissipation can be reduced in the XC95144 by con-
figuring macrocells to standard or low-power modes of
operation. Unused macrocells are turned off to minimize
power dissipation.
Operating current for each design can be approximated for
specific operating conditions using the following equation:
ICC (mA) =
MCHP (1.7) + MCLP (0.9) + MC (0.006 mA/MHz) f
Where:
MCHP = Macrocells in high-performance mode
MCLP = Macrocells in low-power mode
MC = Total number of macrocells used
f = Clock frequency (MHz)
Figure 1 shows a typical calculation for the XC95144
device.
600
400
(300)
200
(160)
High Performance
Low Power
(480)
(320)
0 50 100
Clock Frequency (MHz)
X5898B
Figure 1: Typical Icc vs. Frequency for XC95144
December 4, 1998 (Version 4.0)
1




Xilinx

XC95144 Datasheet Preview

XC95144 Datasheet

XC95144 In-System Programmable CPLD

No Preview Available !

XC95144 In-System Programmable CPLD
JTAG Port
3
1
JTAG
Controller
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O/GCK
I/O/GSR
I/O/GTS
3
1
2
I/O
Blocks
In-System Programming Controller
36
18
36
18
36
18
36
18
Function
Block 1
Macrocells
1 to 18
Function
Block 2
Macrocells
1 to 18
Function
Block 3
Macrocells
1 to 18
Function
Block 4
Macrocells
1 to 18
36
18
Function
Block 8
Macrocells
1 to 18
Figure 2: XC95144 Architecture
Function Block outputs (indicated by the bold line) drive the I/O Blocks directly.
X5922
2 December 4, 1998 (Version 4.0)


Part Number XC95144
Description XC95144 In-System Programmable CPLD
Maker Xilinx
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XC95144 Datasheet PDF





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