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XC95144 Datasheet XC95144 In-System Programmable CPLD

Manufacturer: Xilinx (now AMD)

Overview: 1 ® XC95144 In-System Programmable CPLD 1 1* December 4, 1998 (Version 4.0) Product Specification Operating current for each design can be approximated for specific operating conditions using the following equation: ICC (mA) = MCHP (1.7) + MCLP (0.9) + MC (0.006 mA/MHz) f Where: MCHP = Macrocells in high-performance mode MCLP = Macrocells in low-power mode MC = Total number of macrocells used f = Clock frequency (MHz) Figure 1 shows a typical calculation for the XC95144 device.

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General Description

The XC95144 is a high-performance CPLD providing advanced in-system programming and test capabilities for general purpose logic integration.

It is comprised of eight 36V18 Function Blocks, providing 3,200 usable gates with propagation delays of 7.5 ns.

See Figure 2 for the architecture overview.

Key Features

  • 7.5 ns pin-to-pin logic delays on all pins fCNT to 111 MHz 144 macrocells with 3,200 usable gates Up to 133 user I/O pins 5 V in-system programmable - Endurance of 10,000 program/erase cycles - Program/erase over full commercial voltage and temperature range Enhanced pin-locking architecture Flexible 36V18 Function Block - 90 product terms drive any or all of 18 macrocells within Function Block - Global and product term clocks, output enables, se.

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