XC95216 Datasheet | Xilinx

 XC95216 In-System Programmable CPLD 1 0- August 21, 2001 (Version 3.1) Product Specification Features - - - - - 10 ns pin-to-pin logic delays on all pins f CNT to 111 MHz 216 macrocells with 4800 usable gates Up to 166 user I/O pins 5 V in-system programmable - Endurance of 10,000 program/erase cycles - Program/erase over full mercial voltage and temperature range Enhanced pin-locking architecture Flexible 36V18 Function Block - 90 product terms drive any or all of 18 macrocells within Function Block - Global and product term clocks, output enables, set and reset signals Extensive IEEE Std 1149.1 boundary-scan (JTAG) support Programmable power reduction mode in each macrocell Slew rate control on individual outputs User programmable ground pin capability Extended pattern security Features for design protection High-drive 24 m A outputs 3.3 V or 5 V I/O capability Advanced CMOS 5V Fast FLASH technology Supports parallel programming of more than one XC9500 concurrently Available in 160-pin PQFP, 352-pin BGA, and 208-pin HQFP packages Power Management Power dissipation can be reduced in the XC95216 by configuring macrocells to standard or low-power modes of operation. Unused macrocells are turned off to minimize power dissipation. Operating current for each design can be approximated for specific operating conditions using the following equation: ICC (m A) = MCHP (1.7) + MCLP (0.9) + MC (0.006 m A/MHz) f Where: MCHP = Macrocells in high-performance mode MCLP = Macrocells in low-power mode MC = Total number of macrocells used f = Clock frequency (MHz) Figure 1 shows a typical calculation for the XC95216 device. - - - - - - - - - - - - 600 erf High P orman ce (500) Typical ICC (m A) 400 (360) (340) Description The XC95216 is a high-performance CPLD providing advanced in-system programming and test capabilities for general purpose logic integration. It is prised of twelve 36V18 Function Blocks, providing 4,800 usable gates with propagation delays of...