* of both PLA and PAL type structures to deliver high speed and flexible logic allocation that results in superior ability to make design changes with fixed pinouts. The XPLA structure in each logic block provides a fast 7.5 ns PAL path with five dedicated product terms per output. This PAL path is jo
XCR5064
Xilinx
461.14 KB
64 macrocell cpld with enhanced clocking.
APPLICATION NOTE 0 R XCR5064C: 64 Macrocell CPLD with Enhanced Clocking 0 14 DS044 (v1.1) February 10, 2000 Product Specification speed and z.
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