CLA80000 - High Density CMOS Gate Arrays

Zarlink Semiconductor

Datasheet Details

Part number	CLA80000
Manufacturer	Zarlink Semiconductor
File Size	440.92 KB
Description	High Density CMOS Gate Arrays
Datasheet	CLA80000_ZarlinkSemiconductor.pdf

I I I I I I I I I I 0.7µ (0.8µ drawn) process Typical gate delay 210ps Accurate simulation delay (multi platform support) Support for industry standard workstations Comprehensive cell library 3V option for low power operation Split rail operation (optional 5V I/O, 3V core logic) Low skew clock distribution strategy Power and ground distribution grids Extensive range of package options.

📁 CLA80000 Similar Datasheet

Other Datasheets by Zarlink Semiconductor

Published: Apr 24, 2006 |