Low power channelless arrays from 5,000 to 250,000 available gates (5ยต W / gate / MHz) 1 micron (0.8 micron effective) twin well epitaxial process Typical gate delays of 400 ps (NAND2 , Fanout=2) Comprehensive cell library including DSP, JTAG/BIST and compiled memory cells (ROM blocks to 64K bits and RAM blocks to 16K bits) Extensive Range of Plastic and Ceramic Packages for both Surface Mount and Through Board Assembly Flexible I/O structure allows user t.
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CLA70000 Series
High Density CMOS Gate Arrays
DS2462
ISSUE 3.1
March 1992
Recent advances in CMOS processing technology and improvements in design architecture have led to the development of a new generation of array-based ASIC products with vastly improved gate integration densities. This family of CLA70000 1 micron CMOS arrays brings considerable advantages to the design of next generation systems combining high performance and high complexity.
Overview
The CLA70000 gate array family is Zarlink Semiconductors' sixth generation CMOS gate array product. The family consists of nine arrays implemented on the latest generation (1 micron) twin well epitaxial CMOS process.
CLA70000 Datasheet
