Overview: ( DataSheet : .. ) CLA70000 Series
High Density CMOS Gate Arrays DS2462 ISSUE 3.1 March 1992 Recent advances in CMOS processing technology and improvements in design architecture have led to the development of a new generation of array-based ASIC products with vastly improved gate integration densities. This family of CLA70000 1 micron CMOS arrays brings considerable advantages to the design of next generation systems bining high performance and high plexity. Overview
The CLA70000 gate array family is Zarlink Semiconductors' sixth generation CMOS gate array product. The family consists of nine arrays implemented on the latest generation (1 micron) twin well epitaxial CMOS process. The process in conjunction with the advanced layout and route software, offers extremely high packing densities. The array architecture is based upon the earlier well proven CLA60000 series with the emphasis being placed on high speed, high packing density, and provision of prehensive cell libraries. The cell libraries enpass new DSP and other specialized macros. Full design support is available for major industry standard ASIC design software tools, as well as Zarlink Semiconductor’s proprietary PDS2 design environment. Design support is provided by Zarlink Semiconductor’s design centers, each offering a variety of design routes, which may be customized to individual customer requirements.
