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CLA80000 - High Density CMOS Gate Arrays

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Features

  • I I I I I I I I I I 0.7µ (0.8µ drawn) process Typical gate delay 210ps Accurate simulation delay (multi platform support) Support for industry standard workstations Comprehensive cell library 3V option for low power operation Split rail operation (optional 5V I/O, 3V core logic) Low skew clock distribution strategy Power and ground distribution grids Extensive range of package options.

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Datasheet Details

Part number CLA80000
Manufacturer Zarlink Semiconductor
File Size 440.92 KB
Description High Density CMOS Gate Arrays
Datasheet download datasheet CLA80000 Datasheet
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( DataSheet : www.DataSheet4U.com ) CLA80000 Series High Density CMOS Gate Arrays DS3820 ISSUE 2.1 July 1997 INTRODUCTION The CLA80k gate array series from Zarlink Semiconductor offers advantages in speed and density over previous array series. Improvements in design combined with advances in simulation accuracy allow the implementation of complex systems in excess of 260,000 gates. ARRAY SIZES The CLA80k series comprises 9 base arrays and 22 variants ranging from 2816 to 513,136 array elements. The optimum array for your requirement may be selected from the tables below.
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