MT9046 - T1/E1 System Synchronizer with Holdover

Zarlink Semiconductor

Datasheet Details

Part number	MT9046
Manufacturer	Zarlink Semiconductor
File Size	508.51 KB
Description	T1/E1 System Synchronizer with Holdover
Datasheet	MT9046 Datasheet

General Description

The MT9046 T1/E1 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization signals for multitrunk T1 and E1 primary rate transmission links.

The device has reference switching and frequency holdover capabilities to help maintain connectivity during temporary synchronization interruptions.

LOCK VDD VSS Master Clock TCK TDI TMS TRST TDO PRI SEC IEEE 1149.1a TIE Corrector Circuit Virtual Reference DPLL Output Interface Circuit Reference Select MUX Selected Reference TIE Corrector Enable Reference Select State Select Input Impairment Monitor State Select C19o C1.5o C2o C4o C6o C8o C16o F0o F8o F16o RSP TSP RSEL Control State Machine Feedback Frequency Select MUX MS1 MS2 RST HOLDOVER PCCi FLOCK FS1 FS2 Figure 1 - Functional Block Diagram Zarlink Semiconductor US Patent No.

Overview

MT9046 T1/E1 System Synchronizer with Holdover Data Sheet.

Key Features

Supports AT&T TR62411 and Bellcore GR-1244CORE, Stratum 4 Enhanced and Stratum 4 timing for DS1 interfaces Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 timing for E1 interfaces Selectable 19.44 MHz, 1.544 MHz, 2.048 MHz or 8kHz input reference signals Provides C1.5, C2, C4, C6, C8, C16, and C19 (STS-3/OC3 clock divided by 8) output clock signals Provides 5 styles of 8 KHz framing pulses Holdover frequency accuracy of 0.2 PPM Holdover indication Attenuates wander from 1.9 Hz Fast.

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