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Zarlink Semiconductor

ZL30414 Datasheet Preview

ZL30414 Datasheet

SONET/SDH Clock Multiplier PLL

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ZL30414
SONET/SDH Clock Multiplier PLL
Features
• Meets jitter requirements of Telcordia GR-253-
CORE for OC-192, OC-48, OC-12, and OC-3
rates
• Meets jitter requirements of ITU-T G.813 for STM-
64, STM-16, STM-4 and STM-1 rates
• Provides four LVPECL differential output clocks at
622.08 MHz
• Provides a CML differential clock at 155.52 MHz
• Provides a single-ended CMOS clock at 19.44
MHz
• Lock Indicator
• Provides enable/disable control of output clocks
• Accepts a CMOS reference at 19.44 MHz
• 3.3 V supply
Applications
• SONET/SDH line cards
• Network Element timing cards
Data Sheet
February 2005
Ordering Information
ZL30414QGC 64 Pin TQFP Trays
ZL30414QGC1 64 Pin TQFP* Trays
*Pb Free Matte Tin
-40°C to +85°C
Description
The ZL30414 is an analog phase-locked loop (APLL)
designed to provide jitter attenuation and rate
conversion for SDH (Synchronous Digital Hierarchy)
and SONET (Synchronous Optical Network)
networking equipment. The ZL30414 generates very
low jitter clocks that meet the jitter requirements of
Telcordia GR-253-CORE OC-192, OC-48, OC-12, OC-
3 rates and ITU-T G.813 STM-64, STM-16, STM-4 and
STM-1 rates.
The ZL30414 accepts a CMOS compatible reference
at 19.44 MHz and generates four LVPECL differential
output clocks at 622.08 MHz, a CML differential
clock at 155.52 MHz and a single-ended CMOS
clock at 19.44 MHz. The output clocks can be
individually enabled or disabled. The ZL30414
provides a LOCK indication.
C19i
C622oEN-A
C622oEN-B
LPF C622oEN-C
C622oEN-D
Frequency
& Phase
Detector
Loop
Filter
State
Machine
Reference
and
Bias Circuit
LOCK
BIAS
VCO
19.44MHz
Frequency
Dividers
and
Clock
Drivers
C622oP/N-A
C622oP/N-B
C622oP/N-C
C622oP/N-D
C155oP/N
C19o
VDD GND VCC
C155oEN
C19oEN
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003-2005, Zarlink Semiconductor Inc. All Rights Reserved.
05




Zarlink Semiconductor

ZL30414 Datasheet Preview

ZL30414 Datasheet

SONET/SDH Clock Multiplier PLL

No Preview Available !

ZL30414
Data Sheet
GND
VCC1
VCC
C155oN
C155oP
GND
VCC2
LPF
GND
GND
BIAS
C155oEN
C622oEN-A
C622oEN-B
C622oEN-C
C622oEN-D
64 62 60 58 56 54 52 50 48
2
65 - EP_GND
46
4
44
6
42
8 ZL30414
40
10
38
12
36
14
34
16
18 20 22 24 26 28 30 32
GND
VCC
VDD
GND
VCC
GND
VDD
GND
NC
GND
GND
LOCK
GND
C19o
VDD
GND
Pin Description
Pin Description Table
Pin #
1
2
3
4
5
6
7
Name
GND
VCC1
VCC
C155oN
C155oP
GND
VCC2
8 LPF
9 GND
10 GND
Figure 2 - TQFP 64 pin (Top View)
Description
Ground. 0 volt
Positive Analog Power Supply. +3.3 V ±10%.
Positive Analog Power Supply. +3.3 V ±10%.
C155 Clock Output (CML). These outputs provide a differential 155.52 MHz
clock.
Ground. 0 volt
Positive Analog Power Supply. +3.3 V ±10%
Low Pass
CF) for the
Filter (Analog).
low pass filter.
Connect
to
this
pin
external
RC
network
(RF
and
Ground. 0 volt
Ground. 0 volt
2
Zarlink Semiconductor Inc.


Part Number ZL30414
Description SONET/SDH Clock Multiplier PLL
Maker Zarlink Semiconductor
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ZL30414 Datasheet PDF






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