ZL30415 Description
The ZL30415 is an analog phase-locked loop (APLL) designed to provide jitter attenuation and rate conversion for SDH (Synchronous Digital Hierarchy) and SONET (Synchronous Optical Network) networking equipment. The ZL30415 generates low jitter output clocks that meet the jitter requirements of Telcordia GR-253-CORE OC-12, OC-3, OC-1 rates and ITU-T G.813 STM-4 and STM-1 rates. The ZL30415 accepts a CMOS patible...
ZL30415 Key Features
- 40°C to +85 °C