Description
The ZL30415 is an analog phase-locked loop (APLL) designed to provide jitter attenuation and rate conversion for SDH (Synchronous Digital Hierarchy) and SONET (Synchronous Optical Network) networking equipment.
Features
- Meets jitter requirements of Telcordia GR-253CORE for OC-12, OC-3, and OC-1 rates Meets jitter requirements of ITU-T G.813 for STM4, and STM-1 rates Provides one differential LVPECL output clock selectable to 19.44 MHz, 38.88 MHz, 77.76 MHz, 155.52 MHz, or 622.08 MHz Provides a single-ended CMOS output clock at 19.44 MHz Accepts a single-ended CMOS reference at 19.44 MHz or a differential LVDS, LVPECL, or CML reference at 19.44 MHz or 77.76 MHz Provides a LOCK indic.
ZL30415 Datasheet
