ZL30414 Datasheet | Zarlink Semiconductor

Features - Meets jitter requirements of Telcordia GR-253CORE for OC-192, OC-48, OC-12, and OC-3 rates Meets jitter requirements of ITU-T G.813 for STM64, STM-16, STM-4 and STM-1 rates Provides four LVPECL differential output clocks at 622.08 MHz Provides a CML differential clock at 155.52 MHz Provides a single-ended CMOS clock at 19.44 MHz Lock Indicator Provides enable/disable control of output clocks Accepts a CMOS reference at 19.44 MHz 3.3 V supply Ordering Information ZL30414QGC 64 Pin TQFP Trays ZL30414QGC1 64 Pin TQFP- Trays - Pb Free Matte Tin -40° C to +85 ° C February 2005 - - - - - - - - Description The ZL30414 is an analog phase-locked loop (APLL) designed to provide jitter attenuation and rate conversion for SDH (Synchronous Digital Hierarchy) and SONET (Synchronous Optical Network) networking equipment. The ZL30414 generates very low jitter clocks that meet the jitter requirements of Telcordia GR-253-CORE OC-192, OC-48, OC-12, OC3 rates and ITU-T G.813 STM-64, STM-16, STM-4 and STM-1 rates. The ZL30414 accepts a CMOS patible reference at 19.44 MHz and generates four LVPECL differential output clocks at 622.08 MHz, a CML differential clock at 155.52 MHz and a single-ended CMOS clock at 19.44 MHz. The output clocks can be individually enabled or disabled. The ZL30414 provides a LOCK indication. Applications - - SONET/SDH line cards Network Element timing cards C622o EN-A C622o EN-B C622o EN-C C622o EN-D C622o P/N-A C19i Frequency & Phase Detector Loop Filter VCO Frequency Dividers and Clock Drivers C622o P/N-B C622o P/N-C C622o P/N-D C155o P/N C19o 19.44MHz State Machine Reference and Bias Circuit LOCK BIAS VDD GND VCC C155o EN C19o EN 05 Figure 1 - Functional Block Diagram Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003-2005, Zarlink Semiconductor Inc. All Rights Reserved. Data Sheet GND VCC1 VCC C155o N C155o P GND VCC2 LPF GND GND BIAS C155o EN C622o...