ZL30414 Description
The ZL30414 is an analog phase-locked loop (APLL) designed to provide jitter attenuation and rate conversion for SDH (Synchronous Digital Hierarchy) and SONET (Synchronous Optical Network) networking equipment. The ZL30414 accepts a CMOS patible reference at 19.44 MHz and generates four LVPECL differential output clocks at 622.08 MHz, a CML differential clock at 155.52 MHz and a single-ended CMOS clock at 19.44 MHz....