ZL30416 Description
The ZL30416 is an Analog Phase-Locked Loop (APLL) designed to provide jitter attenuation and rate conversion for SDH (Synchronous Digital Hierarchy) and SONET (Synchronous Optical Network) networking equipment. The ZL30416 accepts a CMOS patible reference at 19.44 MHz or a differential LVDS, LVPECL or CML reference at 19.44 or 77.76 MHz and generates a differential LVPECL output clock selectable to 19.44, 38.88,...
ZL30416 Key Features
- Low jitter clock outputs suitable for OC-192, OC48, OC-12, OC-3 and OC-1 SONET