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Zarlink Semiconductor

ZL30415 Datasheet Preview

ZL30415 Datasheet

SONET/SDH Clock Multiplier PLL

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ZL30415
SONET/SDH Clock Multiplier PLL
Data Sheet
Features
• Meets jitter requirements of Telcordia GR-253-
CORE for OC-12, OC-3, and OC-1 rates
• Meets jitter requirements of ITU-T G.813 for STM-
4, and STM-1 rates
• Provides one differential LVPECL output clock
selectable to 19.44 MHz, 38.88 MHz, 77.76 MHz,
155.52 MHz, or 622.08 MHz
• Provides a single-ended CMOS output clock at
19.44 MHz
• Accepts a single-ended CMOS reference at
19.44 MHz or a differential LVDS, LVPECL, or
CML reference at 19.44 MHz or 77.76 MHz
• Provides a LOCK indication
• 3.3 V supply
Applications
• SONET/SDH line cards
November 2004
Ordering Information
ZL30415GGC
64 Ball CABGA
-40°C to +85°C
Description
The ZL30415 is an analog phase-locked loop (APLL)
designed to provide jitter attenuation and rate
conversion for SDH (Synchronous Digital Hierarchy)
and SONET (Synchronous Optical Network)
networking equipment. The ZL30415 generates low
jitter output clocks that meet the jitter requirements of
Telcordia GR-253-CORE OC-12, OC-3, OC-1 rates
and ITU-T G.813 STM-4 and STM-1 rates.
The ZL30415 accepts a CMOS compatible reference
at 19.44 MHz or a differential LVDS, LVPECL, or CML
reference at 19.44 MHz or 77.76 MHz and generates a
differential LVPECL output clock selectable to
19.44 MHz, 38.88 MHz, 77.76 MHz, 155.52 MHz, or
622.08 MHz, and a single-ended CMOS clock at
19.44 MHz. The ZL30415 provides a lock indication.
REF_SEL
LPF
FS3 FS2 FS1
C19i
REFinP/N
C19i or C77i
CML, LVDS,
LVPECL input
Reference
Selection
MUX
Frequency
& Phase
Detector
State
Machine
Loop
Filter
VCO
19.44 MHz and 77.76 MHz
Reference
and
Bias Circuit
Frequency
Dividers
and
Clock
Drivers
REF_FREQ LOCK
BIAS
VCC GND VDD
C19oEN
C19o, C38o, C77o,
C155o, C622o,
LVPECL output
OC-CLKoP/N
C19o
03
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003-2004, Zarlink Semiconductor Inc. All Rights Reserved.




Zarlink Semiconductor

ZL30415 Datasheet Preview

ZL30415 Datasheet

SONET/SDH Clock Multiplier PLL

No Preview Available !

ZL30415
Data Sheet
12345678
1
A
NC NC
NC OC-CLKoP OC-CLKoN GND NC
NC
B
NC NC VCC1 GND NC GND GND VCC
C
GND VCC2 GND GND GND NC VDD GND
D
BIAS LPF NC GND VCC VCC GND GND
E
LOCK NC
NC FS2
VCC VDD
NC REFinN
F
NC NC REF_FREQ C19oEN C19i C19o GND REFinP
G
GND VDD REF_SEL FS3 GND GND VDD VDD
H
NC NC NC VDD FS1 VDD GND GND
1 - A1 corner is identified by metallized markings.
8 mm x 8 mm
Ball Pitch 0.8 mm
1.0 Ball Description
Ball Description Table
Ball #
A1, A2
A3
A4
A5
Name
NC
OC-CLKoP
OC-CLKoN
A6
A7, A8
B1, B2
B3
B4
B5
GND
NC
VCC1
GND
NC
Figure 2 - BGA 64 Ball Package (Top View)
Description
No internal bonding Connection. Leave unconnected.
SONET/SDH Clock (LVPECL Output). These outputs provide a selectable
differential LVPECL clock at 19.44 Hz, 38.88 MHz, 77.76 MHz, 155.52 MHz,
and 622.08 MHz. The output frequency is selected with FS3, FS2 and FS1
inputs.
Ground. 0 volt
No internal bonding Connection. Leave unconnected.
Positive Analog Power Supply. +3.3 V +/-10%
Ground. 0 volt
No internal bonding Connection. Leave unconnected.
2
Zarlink Semiconductor Inc.


Part Number ZL30415
Description SONET/SDH Clock Multiplier PLL
Maker Zarlink Semiconductor
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ZL30415 Datasheet PDF






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