* Double-data-rate architecture; two data transfers per clock cycle
* The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture
* Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the re
A3R56E40ABF Datasheet (1.53 MB)
A3R56E40ABF
Zentel
1.53 MB
256mb ddrii synchronous dram.
A3R56E40ABF 256Mb DDRII Synchronous DRAM 256Mb DDRII SDRAM Specification A3R56E40ABF Zentel Electronics Corp. Revision 1.2 Dec., 2012 A3R56E40ABF .
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