Datasheet4U Logo Datasheet4U.com

74AC11112 - DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS

📥 Download Datasheet

Preview of 74AC11112 PDF
datasheet Preview Page 2 datasheet Preview Page 3

74AC11112 Product details

Description

1CLK 1CLR NC V CC 2CLR These devices contain two independent J-K negative-edge-triggered flip-flops.A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs regardless of the levels of the other inputs.When preset and clear are inactive (high), data at the J and K inputs meeting the setup time requirements are transferred to the outputs on the negative-going edge of the clock pulse.Clock triggering occurs at a voltage level and is not directly related to the fall tim

📁 74AC11112 Similar Datasheet

  • 74AC11132 - QUAD 2 INPUT NAND SCHMITT TRIGGER (Philips)
  • 74AC11153 - DUAL 4 INPUT MULTIPLEXER (Philips)
  • 74AC11157 - QUAD 2 INPUT MULTIPLEXER (Philips)
  • 74AC11158 - QUAD 2 INPUT MULTIPLEXER (Philips)
  • 74AC11160 - SYNCHRONOUS BCD DECADE COUNTER (Philips)
  • 74AC11181 - 4-BIT ARITHMETIC LOGIC UNIT (Philips)
  • 74AC11190 - ASYNCHRONOUS PRESETTABLE SYNCHRONOUS DECADE UP/DOWN COUNTER (Philips)
  • 74AC11 - TRIPLE 3-INPUT AND GATE (STMicroelectronics)
Other Datasheets by Texas Instruments
  • 74AC11109 - Dual J-K Positive-edge-Triggered Flip-Flops
  • 74AC11138 - 3-Line To 8-Line Decoder/Demultiplexer
  • 74AC11151 - 1-of-8 Data Selector/Multiplexer
  • 74AC11162 - SYNCHRONOUS 4-BIT DECADE COUNTER
  • 74AC11174 - HEX D-TYPE FLIP-FLOP
  • 74AC11175 - QUADRUPLE D-TYPE FLIP-FLOPS
Published: |