ADS5295 Datasheet | Texas Instruments

FEATURES - 2 Maximum Sample Rate: 100 MSPS - Designed for Low Power: - 80 m W per channel at 100 MSPS - SNR: 70.6 d BFS - SFDR: 85 d Bc at 10 MHz, 100 MSPS - Serial LVDS ADC Data Outputs: - One- or Two-Wire Serialized LVDS Outputs per Channel - One-Wire Interface: Up to 80 MSPS Sample Rate - Two-Wire Interface: Up to 100 MSPS Sample Rate - Digital Processing Block: - Programmable FIR Decimation Filter and Oversampling to Minimize Harmonic Interference - Programmable IIR High-Pass Filter to Minimize DC Offset - Programmable Digital Gain: 0 d B to 12 d B - Low-Frequency Noise Suppression Mode - Programmable Mapping Between ADC Input Channels and LVDS Output Pins - Channel Averaging Mode - Variety of LVDS Test Patterns to Verify Data Capture by FPGA or Receiver - Package: 12-mm × 12-mm QFP-80 APPLICATIONS - Ultrasound Imaging - munication Applications - Multichannel Data Acquisition DESCRIPTION The ADS5295 is a low-power, 12-bit, 100-MSPS, 8channel analog-to-digital converter (ADC). Low power consumption and integration of multiple channels in a pact package make the device attractive for very high channel count data acquisition systems. Serial low-voltage differential signaling (LVDS) outputs reduce the number of interface lines and enable high system integration. The ADC digital data can be output over one or two wires of LVDS pins per channel. At high sample rates, the two-wire interface helps keep the serial data rate low, allowing low-cost field-programmable gate array (FPGA)-based receivers to be used. The device integrates an internal reference trimmed to accurately match across devices. Best performance is expected to be achieved through the internal reference mode. However, the device can be driven with external references as well. Several digital functions that are monly used in systems are included in the device. These functions include a low-frequency suppression mode, digital filtering options, and programmable mapping. For low input frequency applications,...