ADS61JB23 Datasheet | Texas Instruments

FEATURES - Output Interface: - Single-Lane and Dual-Lane Interfaces - Maximum Data Rate of 1.6 Gbps - Meets JESD204A Specification - CML Outputs with Current Programmable from 2 m A - 32 m A - Power Dissipation: - 440 m W at 80 MSPS in Single Lane Mode - Power Scales Down with Clock Rate - Input Interface: Buffered Analog Inputs - 71.7 d BFS SNR at 70 MHz IF - Analog Input FSR: 2 Vpp - External and Internal (trimmed) Reference Support - 1.8V Supply (Analog and digital), 3.3 V Supply for Input Buffer - Programmable Digital Gain: 0d B - 6d B - Straight Offset Binary or Twos plement Output - Package: - 6 mm x 6 mm QFN-40 APPLICATIONS - Wireless Base-station Infrastructure - Test and Measurement Instrumentation DESCRIPTION The ADS61JB23 is a high-performance, low-power, single channel analog-to-digital converter with an integrated JESD204A output interface. Available in a 6 mm x 6 mm QFN package, with both single-lane and dual-lane output modes, the ADS61JB23 offers an unprecedented level of pactness. The output interface is patible to the JESD204A standard, with an additional mode (as per IEEE Std 802.3-2002 part3, Clause 36.2.4.12) to interface seamlessly to the TI TLK family of SERDES transceivers. Equally impressive is the inclusion of an onchip analog input buffer, providing isolation between the sample/hold switches and higher and more consistent input impedance. The ADS61JB23 is specified over the industrial temperature range (- 40°C to 85°C). Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2012, Texas Instruments Incorporated SLOS755...