ADS62C15 Datasheet | Texas Instruments

FEATURES - Maximum Sample Rate: 125 MSPS - 11-Bit Resolution With No Missing Codes - 82 d Bc SFDR at Fin = 117 MHz - 67 d BFS SNR at Fin = 117 MHz - 77.5 d BFS SNR at Fin = 117 MHz, 20MHz bandwidth using SNRBoost technology - 92 d B Crosstalk - Parallel CMOS and DDR LVDS Output Options - 3.5 d B Coarse Gain and Programmable Fine Gain up to 6 d B for SNR/SFDR Trade-Off - Digital Processing Block With: - Offset Correction - Fine Gain Correction, in Steps of 0.05 d B - Decimation by 2/4/8 - Built-in and Custom Programmable 24-Tap Low/High /Band Pass Filters - Supports Sine, LVPECL, LVDS and LVCMOS Clocks and Amplitude Down to 400 m VPP - Clock Duty Cycle Stabilizer - Internal Reference; Also Supports External Reference - 64-QFN Package (9mm × 9mm) APPLICATIONS - Wireless munications Infrastructure - Software Defined Radio - Power Amplifier Linearization - 802.16d/e - Medical Imaging - Radar Systems - Test and Measurement Instrumentation DESCRIPTION ADS62C15 is a dual channel 11-bit A/D converter with maximum sample rates up to 125 MSPS. It bines high performance and low power consumption in a pact 64 QFN package. Using an internal sample and hold and low jitter clock buffer, the ADC supports high SNR and high SFDR at high input frequencies. It has coarse and fine gain options that can be used to improve SFDR performance at lower full-scale input ranges. ADS62C15 uses proprietary SNRBoost technology that can be used to overe SNR limitation due to quantization noise (for bandwidths less than Nyquist, Fs/2). It includes a digital processing block that consists of several useful and monly used digital functions such as ADC offset correction, fine gain correction (in steps of 0.05 d B), decimation by 2,4,8 and in-built and custom programmable filters. By default, the digital processing block is bypassed, and its functions are disabled. Two output interface options exist - parallel CMOS and DDR LVDS (Double Data Rate). ADS62C15 includes internal references while traditional...