ADS6222 Datasheet PDF - Texas Instruments Analog-to-Digital Converters Specs

ADS6222 - Analog-to-Digital Converters

Datasheet Summary

Description

ADS6225/ADS6224/ADS6223/ADS6222 (ADS622X) is a family of high performance 12-bit 125/105/80/65 MSPS dual channel A-D converters.

Serial LVDS data outputs reduce the number of interface lines, resulting in a compact 48-pin QFN package (7 mm × 7 mm) that allows for high system integration density.

Features

1.
Maximum Sample Rate: 125 MSPS.
12-Bit Resolution with No Missing Codes.
Simultaneous Sample and Hold.
3.5 dB Coarse Gain and up to 6 dB Programmable Fine Gain for SFDR/SNR TradeOff.
Serialized LVDS Outputs with Programmable Internal Termination Option.
Supports Sine, LVCMOS, LVPECL, LVDS Clock Inputs and Amplitude Down to 400 mVpp.
Internal Reference with External Reference Support.
No External Decoupling Required for Ref.

Datasheet Details

Part number	ADS6222
Manufacturer	Texas Instruments
File Size	3.85 MB
Description	Analog-to-Digital Converters
Datasheet	ADS6222 Datasheet
Additional preview pages of the ADS6222 datasheet.

📁 Similar Datasheet

ADS60C100L - 3 Quadrants Triacs (ADV)

ADS60C100S - 3 Quadrants Triacs (ADV)

ADS60C120L - 3 Quadrants Triacs (ADV)

ADS60C120S - 3 Quadrants Triacs (ADV)

ADS60C160L - 3 Quadrants Triacs (ADV)

ADS60C160S - 3 Quadrants Triacs (ADV)

ADS6608A4A - Synchronous DRAM (A-Data Technology)

ADS6616A4A - Synchronous DRAM (A-Data Technology)

ADS6632A4A - Synchronous DRAM (A-Data Technology)

ADS6C60 - 3 Quadrants Triacs (ADV)

Full PDF Text Transcription

Click to expand full text

ADS6225, ADS6224 ADS6223, ADS6222 www.ti.com SLAS543B – MAY 2007 – REVISED JANUARY 2014 DUAL CHANNEL, 12-BIT, 125/105/80/65 MSPS ADC WITH SERIAL LVDS INTERFACE Check for Samples: ADS6225, ADS6224, ADS6223, ADS6222 FEATURES 1 • Maximum Sample Rate: 125 MSPS • 12-Bit Resolution with No Missing Codes • Simultaneous Sample and Hold • 3.5 dB Coarse Gain and up to 6 dB Programmable Fine Gain for SFDR/SNR TradeOff • Serialized LVDS Outputs with Programmable Internal Termination Option • Supports Sine, LVCMOS, LVPECL, LVDS Clock Inputs and Amplitude Down to 400 mVpp • Internal Reference with External Reference Support • No External Decoupling Required for References • 3.

Published: Mar 6, 2024 |