ADS6242 Overview
Serial LVDS data outputs reduce the number of interface lines, resulting in a pact 48-pin QFN package (7 mm × 7mm) that allows for high system integration density. The device includes 3.5 dB coarse gain option that can be used to improve SFDR performance with little degradation in SNR. In addition to the coarse gain, fine gain options also exist, programmable in 1dB steps up to 6dB.
ADS6242 Key Features
- Maximum Sample Rate: 125 MSPS
- 14-Bit Resolution with No Missing Codes
- Simultaneous Sample and Hold
- 3.5 dB Coarse Gain and up to 6 dB
- Serialized LVDS Outputs with Programmable Internal Termination Option
- Supports Sine, LVCMOS, LVPECL, LVDS Clock Inputs and Amplitude down to 400 mVpp
- Internal Reference with External Reference Support
- No External Decoupling Required for References
- 3.3-V Analog and Digital Supply
- 48 QFN Package (7 mm × 7 mm)