ADS6223 Datasheet | Texas Instruments

FEATURES - Maximum Sample Rate: 125 MSPS - 12-Bit Resolution with No Missing Codes - Simultaneous Sample and Hold - 3.5 d B Coarse Gain and up to 6 d B Programmable Fine Gain for SFDR/SNR Trade Off - Serialized LVDS Outputs with Programmable Internal Termination Option - Supports Sine, LVCMOS, LVPECL, LVDS Clock Inputs and Amplitude Down to 400 m Vpp - Internal Reference with External Reference Support - No External Decoupling Required for References - 3.3-V Analog and Digital Supply - 48 QFN Package (7 mm × 7 mm) - Pin patible 14-Bit Family (ADS624X SLAS542) - Feature patible Quad Channel Family (ADS644X - SLAS531 and ADS642X - SLAS532) APPLICATIONS - Base-Station IF Receivers - Diversity Receivers - Medical Imaging - Test Equipment Table 1. ADS62XX Dual Channel Family ADS624X 14 Bit ADS622X 12 Bit 125 MSPS 105 MSPS 80 MSPS 65 MSPS ADS6245 ADS6244 ADS6243 ADS6242 ADS6225 ADS6224 ADS6223 ADS6222 Table 2. Performance Summary SFDR, d Bc Fin = 10MHz (0 d B gain) Fin = 170MHz (3.5 d B gain) Fin = 10MHz (0 d B gain) SINAD, d BFS Fin = 170MHz (3.5 d B gain) Power per channel, m W ADS6225 90 79 70.7 67.4 500 ADS6224 91 81 70.8 68.1 405 ADS6223 91 82 71.3 68.2 350 ADS6222 93 83 71.3 68.7 315 DESCRIPTION ADS6225/ADS6224/ADS6223/ADS6222 (ADS622X) is a family of high performance 12-bit 125/105/80/65 MSPS dual channel A-D converters. Serial LVDS data outputs reduce the number of interface lines, resulting in a pact 48-pin QFN package (7 mm × 7 mm) that allows for high system integration density. The device includes 3.5 d B coarse gain option that can be used to improve SFDR performance with little degradation in SNR. In addition to the coarse gain, fine gain options also exist, programmable in 1 d B steps up to 6 d B. The output interface is 2-wire, where each ADC data is serialized and output over two LVDS pairs. This makes it possible to halve the serial data rate (pared to a 1-wire interface) and restrict it to less than 1 Gbps easing receiver design. The ADS622X also...