AM5K2E02 Datasheet | Texas Instruments

Product Folder Sample & Buy Technical Documents Tools & Software Support & munity AM5K2E04, AM5K2E02 SPRS864D - NOVEMBER 2012 - REVISED MARCH 2015 AM5K2E0x Multicore ARM Key Stone II System-on-Chip (So C) 1 AM5K2E0x Features and Description 1.1 Features - ARM® Cortex®-A15 MPCore™ Core Pac - Up to Four ARM Cortex-A15 Processor Cores at up to 1.4-GHz - 4MB L2 Cache Memory Shared by all Cortex A15 Processor Cores - Full Implementation of ARMv7-A Architecture Instruction Set - 32KB L1 Instruction and Data Caches per Core - AMBA 4.0 AXI Coherency Extension (ACE) Master Port, Connected to MSMC (Multicore Shared Memory Controller) for Low Latency Access to SRAM and DDR3 - Multicore Shared Memory Controller (MSMC) - 2 MB SRAM Memory for ARM Core Pac - Memory Protection Unit for Both SRAM and DDR3_EMIF - Multicore Navigator - 8k Multi-Purpose Hardware Queues with Queue Manager - One Packet-Based DMA Engine for Zero Overhead Transfers - Network Coprocessor - Packet Accelerator Enables Support for - Transport Plane IPsec, GTP-U, SCTP, PDCP - L2 User Plane PDCP (Ro HC, Air Ciphering) - 1 Gbps Wire Speed Throughput at 1.5 MPackets Per Second - Security Accelerator Engine Enables Support...