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AM5K2E02 Datasheet Preview

AM5K2E02 Datasheet

Multicore ARM KeyStoneII System-on-Chip

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AM5K2E04, AM5K2E02
SPRS864D – NOVEMBER 2012 – REVISED MARCH 2015
AM5K2E0x Multicore ARM KeyStone II System-on-Chip (SoC)
1 AM5K2E0x Features and Description
1.1 Features
1
• ARM® Cortex®-A15 MPCore™ CorePac
– Up to Four ARM Cortex-A15 Processor Cores at
up to 1.4-GHz
– 4MB L2 Cache Memory Shared by all Cortex-
A15 Processor Cores
– Full Implementation of ARMv7-A Architecture
Instruction Set
– 32KB L1 Instruction and Data Caches per Core
– AMBA 4.0 AXI Coherency Extension (ACE)
Master Port, Connected to MSMC (Multicore
Shared Memory Controller) for Low Latency
Access to SRAM and DDR3
• Multicore Shared Memory Controller (MSMC)
– 2 MB SRAM Memory for ARM CorePac
– Memory Protection Unit for Both SRAM and
DDR3_EMIF
• Multicore Navigator
– 8k Multi-Purpose Hardware Queues with Queue
Manager
– One Packet-Based DMA Engine for Zero-
Overhead Transfers
• Network Coprocessor
– Packet Accelerator Enables Support for
• Transport Plane IPsec, GTP-U, SCTP,
PDCP
• L2 User Plane PDCP (RoHC, Air Ciphering)
• 1 Gbps Wire Speed Throughput at 1.5
MPackets Per Second
– Security Accelerator Engine Enables Support for
• IPSec, SRTP, 3GPP and WiMAX Air
Interface, and SSL/TLS Security
• ECB, CBC, CTR, F8, A5/3, CCM, GCM,
HMAC, CMAC, GMAC, AES, DES, 3DES,
Kasumi, SNOW 3G, SHA-1, SHA-2 (256-bit
Hash), MD5
• Up to 6.4 Gbps IPSec and 3 Gbps Air
Ciphering
– Ethernet Subsystem
• Eight SGMII Ports with Wire Rate Switching
• IEEE1588 v2 (with Annex D/E/F) Support
• 8 Gbps Total Ingress/Egress Ethernet BW
from Core
• Audio/Video Bridging (802.1Qav/D6.0)
• QOS Capability
• DSCP Priority Mapping
• Peripherals
– Two PCIe Gen2 Controllers with Support for
• Two Lanes per Controller
• Supports Up to 5 GBaud
– One HyperLink
• Supports Connections to Other KeyStone
Architecture Devices Providing Resource
Scalability
• Supports Up to 50 GBaud
– 10-Gigabit Ethernet (10-GbE) Switch Subsystem
• Two SGMII/XFI Ports with Wire Rate
Switching and MACSEC Support
• IEEE1588 v2 (with Annex D/E/F) Support
– One 72-Bit DDR3/DDR3L Interface with Speeds
Up to 1600 MTPS in DDR3 Mode
– EMIF16 Interface
– Two USB 2.0/3.0 Controllers
– USIM Interface
– Two UART Interfaces
– Three I2C Interfaces
– 32 GPIO Pins
– Three SPI Interfaces
– One TSIP
• Support 1024 DS0s
• Support 2 Lanes at 32.768/16.3848.192
Mbps Per Lane
• System Resources
– Three On-Chip PLLs
– SmartReflex Automatic Voltage Scaling
– Semaphore Module
– Twelve 64-Bit Timers
– Five Enhanced Direct Memory Access (EDMA)
Modules
• Commercial Case Temperature:
– 0ºC to 85ºC
• Extended Case Temperature:
– -40ºC to 100ºC
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.




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AM5K2E02 Datasheet Preview

AM5K2E02 Datasheet

Multicore ARM KeyStoneII System-on-Chip

No Preview Available !

AM5K2E04, AM5K2E02
SPRS864D – NOVEMBER 2012 – REVISED MARCH 2015
www.ti.com
1.2 Applications
• Avionics and Defense
• Communications
• Industrial Automation
• Automation and Process Control
• Servers
• Enterprise Networking
• Cloud Infrastructure
1.3 KeyStone II Architecture
TI's KeyStone II Multicore Architecture provides a unified platform for integrating RISC processing cores
along with both hardware/firmware based application-specific acceleration and high performance I/Os. The
KeyStone II Multicore Architecture is a proven device architecture to achieve the full performance
entitlement through the following major components: TeraNet, Multicore Shared Memory Controller,
Multicore Navigator, and HyperLink.
TeraNet is a multipoint to multipoint non-blocking switch fabric. Its distributed arbiter provides multiple
duplex communication channels in parallel between the master and slave ports without interference. The
priority based arbitration mechanism ensures the delivery of the critical traffic delivery in the system.
The Multicore Shared Memory Controller (MSMC) is the center of the KeyStone II memory architecture. It
provides multiple fast and high-bandwidth channels for processor cores to access DDR and minimizes the
access latency by directly connecting to the DDR. The MSMC also provides the flexibility to expand
processor cores with little impact at the device level. In addition, it provides multi-bank based fast on-chip
SRAM shared among processor cores and IOs. It also provides the I/O cache coherency for the device
when the Cortex-A15 processor core is integrated.
The Multicore Navigator provides a packet-based IPC mechanism among processing cores and packet
based peripherals. The hardware-managed queues supports multiple-in-multiple-out mode without using
mutex. Coupled with the packet-based DMA, the Multicore Navigator provides a highly efficient and
software-friendly tool to offload the processing core to achieve other critical tasks.
HyperLink provides a 50-GBaud chip-level interconnect that allows devices to work in tandem. Its low
latency, low overhead and high throughput makes it an ideal interface for chip-to-chip interconnections.
There are two generations of KeyStone architecture. The AM5K2E0x device is based on KeyStone II,
which integrates a Cortex-A15 processor CorePac.
1.4 Device Description
The AM5K2E0x is a high performance device based on TI's KeyStone II Multicore SoC Architecture,
incorporating the most performance-optimized Cortex-A15 processor dual-core or quad-core CorePac that
can run at a core speed of up to 1.4 GHz. TI's AM5K2E0x device enables a high performance, power-
efficient and easy to use platform for developers of a broad range of applications such as enterprise grade
networking end equipment, data center networking, avionics and defense, medical imaging, test and
automation.
TI's KeyStone II Architecture provides a programmable platform integrating various subsystems (for
example, ARM CorePac (Cortex-A15 Processor Quad Core CorePac), network processing, and uses a
queue-based communication system that allows the device resources to operate efficiently and
seamlessly. This unique device architecture also includes a TeraNet switch that enables the wide mix of
system elements, from programmable cores to high-speed IO, to each operate at maximum efficiency with
no blocking or stalling.
The AM5K2E0x KeyStone II device integrates a large amount of on-chip memory. The Cortex-A15
processor cores each have 32KB of L1Data and 32KB of L1 Instruction cache. The up to four Cortex A15
cores in the ARM CorePac share a 4MB L2 Cache. The device also integrates 2MB of Multicore Shared
Memory (MSMC) that can be used as a shared L3 SRAM. All L2 and MSMC memories incorporate error
detection and error correction. For fast access to external memory, this device includes a 64-bit DDR-3
(72-bit with ECC support) external memory interface (EMIF) running at 1600 MTPS.
2
AM5K2E0x Features and Description
Copyright © 2012–2015, Texas Instruments Incorporated
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Part Number AM5K2E02
Description Multicore ARM KeyStoneII System-on-Chip
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