AM5K2E02
Overview
- 1 Features 1
- ARM® Cortex®-A15 MPCore™ CorePac - Up to Four ARM Cortex-A15 Processor Cores at up to 1.4-GHz - 4MB L2 Cache Memory Shared by all CortexA15 Processor Cores - Full Implementation of ARMv7-A Architecture Instruction Set - 32KB L1 Instruction and Data Caches per Core - AMBA 4.0 AXI Coherency Extension (ACE) Master Port, Connected to MSMC (Multicore Shared Memory Controller) for Low Latency Access to SRAM and DDR3
- Multicore Shared Memory Controller (MSMC) - 2 MB SRAM Memory for ARM CorePac - Memory Protection Unit for Both SRAM and DDR3_EMIF
- Multicore Navigator - 8k Multi-Purpose Hardware Queues with Queue Manager - One Packet-Based DMA Engine for ZeroOverhead Transfers
- Network Coprocessor - Packet Accelerator Enables Support for
- Transport Plane IPsec, GTP-U, SCTP, PDCP
- L2 User Plane PDCP (RoHC, Air Ciphering)
- 1 Gbps Wire Speed Throughput at 1.5 MPackets Per Second - Security Accelerator Engine Enables Support for
- IPSec, SRTP, 3GPP and WiMAX Air Interface, and SSL/TLS Security
- ECB, CBC, CTR, F8, A5/3, CCM, GCM, HMAC, CMAC, GMAC, AES, DES, 3DES, Kasumi, SNOW 3G, SHA-1, SHA-2 (256-bit Hash), MD5
