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CD54HC597 Datasheet Preview

CD54HC597 Datasheet

8-Bit Shift Register

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Data sheet acquired from Harris Semiconductor
SCHS191C
January 1998 - Revised October 2003
CD54HC597, CD74HC597,
CD74HCT597
High-Speed CMOS Logic
8-Bit Shift Register with Input Storage
[ /Title
(CD74
HC597
,
CD74
HCT59
7)
/Sub-
ject
(High
Speed
CMOS
Features
Description
• Buffered Inputs
• Asynchronous Parallel Load
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il 1µA at VOL, VOH
The ’HC597 and CD74HCT597 are high-speed silicon gate
CMOS devices that are pin-compatible with the LSTTL 597
devices. Each device consists of an 8-flip-flop input register
and an 8-bit parallel-in/serial-in, serial-out shift register. Each
register is controlled by its own clock. A “low” on the parallel
load input (PL) shifts parallel stored data asynchronously into
the shift register. A “low” master input (MR) clears the shift
register. Serial input data can also be synchronously shifted
through the shift register when PL is high.
Ordering Information
PART NUMBER
TEMP. RANGE (oC)
PACKAGE
CD54HC597F3A
-55 to 125
16 Ld CERDIP
CD74HC597E
-55 to 125
16 Ld PDIP
CD74HC597M
-55 to 125
16 Ld SOIC
CD74HC597MT
-55 to 125
16 Ld SOIC
CD74HC597M96
-55 to 125
16 Ld SOIC
CD74HC597NSR
-55 to 125
16 Ld SOP
CD74HCT597E
-55 to 125
16 Ld PDIP
CD74HCT597M
-55 to 125
16 Ld SOIC
CD74HCT597MT
-55 to 125
16 Ld SOIC
CD74HCT597M96
-55 to 125
16 Ld SOIC
NOTE: When ordering, use the entire part number. The suffixes 96
and R denote tape and reel. The suffix T denotes a small-quantity
reel of 250.
Pinout
CD54HC597
(CERDIP)
CD74HC597
(PDIP, SOIC, SOP)
CD74HCT597
(PDIP, SOIC)
TOP VIEW
D1 1
D2 2
D3 3
D4 4
D5 5
D6 6
D7 7
GND 8
16 VCC
15 D0
14 DS
13 PL
12 STCP
11 SHCP
10 MR
9 Q7
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
1




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CD54HC597 Datasheet Preview

CD54HC597 Datasheet

8-Bit Shift Register

No Preview Available !

CD54HC597, CD74HC597, CD74HCT597
Functional Diagram
DS
15
D0
1
D1
2
D2
PARALLEL
DATA
INPUTS
3
D3
4 8 F/F
D4 STORAGE
5 REG.
D5
6
D6
7
D7
12
STCP
11
SHCP 13
PL 10
MR
14
8-BIT
SHIFT
REG.
9
Q7
FUNCTION TABLE
STCP
SHCP
PL
X
X
MR
FUNCTION
X
Data Loaded to Input Flip-Flops
X
L
H
Data Loaded from Inputs to Shift Register
No Clock Edge
X
L
H
Data Transferred from Input Flip-Flops to Shift Register
X
X
L
L
Invalid Logic, State of Shift Register Indeterminate when
Signals Removed
X
X
H
L
Shift Register Cleared
X
H
H
Shift Register Clocked Qn = Qn-1, Q0 = DS
H = High Voltage Level, L = Low Voltage Level, X = Don’t Care, = Transition from Low to High CP Level
2


Part Number CD54HC597
Description 8-Bit Shift Register
Maker etcTI
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