CD74HC195 Description
Asynchronous Master Reset J, K, (D) Inputs to First Stage Fully Synchronous Serial or Parallel Data Transfer Shift Right and Parallel Load Capability plementary Output From Last Stage Buffered Inputs CTyLp=ic1a5l pfMF,ATXA==5205MoHCz at VCC = 5V, Fanout (Over Temperature Range) - Standard Outputs . 10 LSTTL Loads - Bus Driver Outputs . 15 LSTTL Loads Wide Operating Temperature Range.
CD74HC195 Key Features
- Asynchronous Master Reset
- J, K, (D) Inputs to First Stage
- Fully Synchronous Serial or Parallel Data Transfer
- Shift Right and Parallel Load Capability
- plementary Output From Last Stage
- Buffered Inputs
- CTyLp=ic1a5l pfMF,ATXA==5205MoHCz at VCC = 5V
- Fanout (Over Temperature Range)
- Standard Outputs
- 10 LSTTL Loads