* Distributes One Differential Clock Input to Three LVPECL Differential Clock Outputs and One LVCMOS Single-Ended Output
* Programmable Output Divider for Two LVPECL Outputs and LVCMOS Output
* Low-Output Skew 15 ps (Typical) for Clock-Distribution Applications for LVPECL Out
CDCM1804
2.19 MB
1:3 lvpecl clock buffer + additional lvcmos output and programmable divider.
www.ti.com CDCM1804 SCAS697E JULY 2003 REVISED MAY 2005 1:3 LVPECL CLOCK BUFFER + ADDITIONAL LVCMOS OUTPUT AND PROGRAMMABLE DIVID.
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