Datasheet Summary
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SCAS697E
- JULY 2003
- REVISED MAY 2005
1:3 LVPECL CLOCK BUFFER + ADDITIONAL LVCMOS OUTPUT AND PROGRAMMABLE DIVIDER
Features
- Distributes One Differential Clock Input to Three LVPECL Differential Clock Outputs and One LVCMOS Single-Ended Output
- Programmable Output Divider for Two LVPECL Outputs and LVCMOS Output
- Low-Output Skew 15 ps (Typical) for Clock-Distribution Applications for LVPECL Outputs; 1.6-ns Output Skew Between LVCMOS and LVPECL Transitions Minimizing Noise
- VCC Range 3 V- 3.6 V
- Signaling Rate Up to 800-MHz LVPECL and
200-MHz LVCMOS
- Differential Input Stage for Wide mon-Mode Range
- Provides VBB Bias Voltage Output for Single-Ended Input...