Datasheet4U Logo Datasheet4U.com

CDCV850I Datasheet 2.5-v Phase Lock Loop Clock Driver

Manufacturer: Texas Instruments

Overview: CDCV850, CDCV850I 2.5ĆV PHASE LOCK LOOP CLOCK DRIVER WITH 2ĆLINE SERIAL INTERFACE SCAS647B − OCTOBER 2000 − REVISED DECEMBER 2002 D Phase-Lock Loop Clock Driver for Double Data-Rate Synchronous DRAM DGG PACKAGE (TOP.

This datasheet includes multiple variants, all published together in a single manufacturer document.

General Description

GND 18 Y3 19 31 GND 30 Y8 The CDCV850 is a high-performance, low-skew, low-jitter zero delay buffer that distributes a differential clock input pair (CLK, CLK) to ten differential pairs of clock outputs (Y[0:9], Y[0:9]) and one differential pair of feedback clock outputs Y3 20 VDDQ 21 Y4 22 Y4 23 GND 24 29 Y8 28 VDDQ 27 Y9 26 Y9 25 GND (FBOUT, FBOUT).

The clock outputs are con- trolled by the clock inputs (CLK, CLK), the feedback clocks (FBIN, FBIN), the 2-line serial interface (SDATA, SCLK), and the analog power input (AVDD).

A two-line serial interface can put the individual output clock pairs in a high-impedance state.

CDCV850I Distributor & Price

Compare CDCV850I distributor prices and check real-time stock availability from major suppliers. Prices and inventory may vary by region and order quantity.

More Datasheets from Texas Instruments

Part Number Description
CDCV850 2.5-V Phase Lock Loop Clock Driver
CDCV855 2.5-V PHASE-LOCK LOOP CLOCK DRIVER
CDCV855I 2.5-V PHASE-LOCK LOOP CLOCK DRIVER
CDCV857A 2.5-V PHASE LOCK LOOP CLOCK DRIVER
CDCV857B 2.5-V PHASE LOCK LOOP CLOCK DRIVER
CDCV857BI 2.5-V PHASE LOCK LOOP CLOCK DRIVER
CDCV304 200-MHz General-Purpose Clock Buffer
CDCV304-EP General-Purpose Clock Buffer
CDCVF111 1:9 DIFFERENTIAL LVPECL CLOCK DRIVER
CDCVF2310 2.5-V to 3.3-V High-Performance Clock Buffer