2.5-v phase lock loop clock driver.
D Spread Spectrum Clock Compatible D Operating Frequency: 60 to 140 MHz D Low Jitter (cyc−cyc): ±75 ps D Distributes One.
GND 18 Y3 19
31 GND 30 Y8
The CDCV850 is a high-performance, low-skew, low-jitter zero delay buffer that distributes a differential clock input pair (CLK, CLK) to ten differential pairs of clock outputs (Y[0:9], Y[0:9]) and one differential pair o.
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