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CDCV857B - 2.5-V PHASE LOCK LOOP CLOCK DRIVER

General Description

The CDCV857B is a high-performance, low-skew, low-jitter zero delay buffer that distributes a differential clock input pair (CLK, CLK) to 10 differential pairs of clock outputs (Y[0:9], Y[0:9]) and one differential pair of feedback clock outputs (FBOUT, FBOUT).

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Other Datasheets by Texas Instruments

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CDCV857BI 2.5-V PHASE LOCK LOOP CLOCK DRIVER
CDCV857A 2.5-V PHASE LOCK LOOP CLOCK DRIVER
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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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CDCV857B, CDCV857BI 2.5ĆV PHASEĆLOCK LOOP CLOCK DRIVER D Phase-Lock Loop Clock Driver for Double Data-Rate Synchronous DRAM Applications D Spread Spectrum Clock Compatible D Operating Frequency: 60 MHz to 200 MHz D Low Jitter (cycle-cycle): ±50 ps D Low Static Phase Offset: ±50 ps D Low Jitter (Period): ±35 ps D Distributes One Differential Clock Input to 10 Differential Outputs SCAS689 − FEBRUARY 2003 D Enters Low-Power Mode When No CLK Input Signal Is Applied or PWRDWN Is Low D Operates From Dual 2.