CDCV850I - 2.5-V Phase Lock Loop Clock Driver

GND 18 Y3 19 31 GND 30 Y8 The CDCV850 is a high-performance, low-skew, low-jitter zero delay buffer that distributes a differential clock input pair (CLK, CLK) to ten differential pairs of clock outputs (Y[0:9], Y[0:9]) and one differential pair of feedback clock outputs Y3 20 VDDQ 21 Y4 22 Y4 2