* 1
* 2 Low jitter 400 Mbps fully differential data path
* 145 ps (typ) of pk-pk jitter with PRBS = 223
* 1 data pattern at 400 Mbps
* Single +3.3 V Supply
* Balanced output impedance
* Output channel-to-channel skew is 35ps (typ)
* Differential out
DS90LV110AT Datasheet (739.97 KB)
DS90LV110AT
739.97 KB
1 to 10 lvds data/clock distributor.
DS90LV110AT www.ti.com SNOSAC2J AUGUST 2004 REVISED APRIL 2013 DS90LV110AT 1 to 10 LVDS Data/Clock Distributor with Failsafe Ch.
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