Datasheet Summary
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SNOSAC2J
- AUGUST 2004
- REVISED APRIL 2013
DS90LV110AT 1 to 10 LVDS Data/Clock Distributor with Failsafe
Check for Samples: DS90LV110AT
Features
- 2 Low jitter 400 Mbps fully differential data path
- 145 ps (typ) of pk-pk jitter with PRBS = 223- 1 data pattern at 400 Mbps
- Single +3.3 V Supply
- Balanced output impedance
- Output channel-to-channel skew is 35ps (typ)
- Differential output voltage (VOD) is 320mV (typ) with 100Ω termination load.
- LVDS receiver inputs accept LVPECL signals
- LVDS input failsafe
- Fast propagation delay of 2.8 ns (typ)
- Receiver open, shorted, and terminated input failsafe
- 28 lead TSSOP package
- Conforms to ANSI/TIA/EIA-644...
