DS90LV110T Datasheet PDF (1 to 10 LVDS Data/Clock Distributor) | Download National Semiconductor DS90LV110T

DS90LV110T - 1 to 10 LVDS Data/Clock Distributor

Description

DS90LV110 is a 1 to 10 data/clock distributor utilizing LVDS (Low Voltage Differential Signaling) technology for low power, high speed operation.

Data paths are fully differential from input to output for low noise generation and low pulse width distortion.

Features

n Low jitter 800 Mbps fully differential data path n 145 ps (typ) of pk-pk jitter with PRBS = 223.
1 data pattern at 800 Mbps n Single +3.3 V Supply n Less than 413 mW (typ) total power dissipation n Balanced output impedance n Output channel-to-channel skew is 35ps (typ) n Differential output voltage (VOD) is 320mV (typ) with 100Ω termination load. n LVDS receiver inputs accept LVPECL signals n Fast propagation delay of 2.8 ns (typ) n Receiver input threshold < ± 100 mV n 28 lead TSSOP p.

Datasheet Details

Part number	DS90LV110T
Manufacturer	National Semiconductor
File Size	468.40 KB
Description	1 to 10 LVDS Data/Clock Distributor
Datasheet	DS90LV110T Datasheet
Additional preview pages of the DS90LV110T datasheet.

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Full PDF Text Transcription

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1 to 10 LVDS Data/Clock Distributor July 2001 DS90LV110T 1 to 10 LVDS Data/Clock Distributor General Description DS90LV110 is a 1 to 10 data/clock distributor utilizing LVDS (Low Voltage Differential Signaling) technology for low power, high speed operation. Data paths are fully differential from input to output for low noise generation and low pulse width distortion. The design allows connection of 1 input to all 10 outputs. LVDS I/O enable high speed data transmission for point-to-point interconnects. This device can be used as a high speed differential 1 to 10 signal distribution / fanout replacing multi-drop bus applications for higher speed links with improved signal quality. It can also be used for clock distribution up to 400MHz.

Published: Mar 30, 2005 |