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DS90LV110AT - 1 to 10 LVDS Data/Clock Distributor

Description

DS90LV110A is a 1 to 10 data/clock distributor utilizing LVDS (Low Voltage Differential Signaling) technology for low power, high speed operation.

Data paths are fully differential from input to output for low noise generation and low pulse width distortion.

Features

  • Low jitter 400 Mbps fully differential data path.
  • 145 ps (typ) of pk-pk jitter with PRBS = 223.
  • 1 data pattern.
  • at 400 Mbps Single +3.3 V Supply Balanced output impedance Output channel-to-channel skew is 35ps (typ) Differential output voltage (VOD) is 320mV (typ) with 100Ω termination load. LVDS receiver inputs accept LVPECL signals LVDS input failsafe Fast propagation delay of 2.8 ns (typ) Receiver open, shorted, and.

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Datasheet preview – DS90LV110AT

Datasheet Details

Part number DS90LV110AT
Manufacturer National Semiconductor
File Size 1.25 MB
Description 1 to 10 LVDS Data/Clock Distributor
Datasheet download datasheet DS90LV110AT Datasheet
Additional preview pages of the DS90LV110AT datasheet.

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DS90LV110AT 1 to 10 LVDS Data/Clock Distributor with Failsafe www.DataSheet4U.com September 19, 2008 DS90LV110AT 1 to 10 LVDS Data/Clock Distributor with Failsafe General Description DS90LV110A is a 1 to 10 data/clock distributor utilizing LVDS (Low Voltage Differential Signaling) technology for low power, high speed operation. Data paths are fully differential from input to output for low noise generation and low pulse width distortion. The design allows connection of 1 input to all 10 outputs. LVDS I/O enable high speed data transmission for point-to-point interconnects. This device can be used as a high speed differential 1 to 10 signal distribution / fanout replacing multi-drop bus applications for higher speed links with improved signal quality.
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