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DS90LV110AT - 1 to 10 LVDS Data/Clock Distributor

Description

DS90LV110A is a 1 to 10 data/clock distributor utilizing LVDS (Low Voltage Differential Signaling) technology for low power, high speed operation.

Data paths are fully differential from input to output for low noise generation and low pulse width distortion.

Features

  • 1.
  • 2 Low jitter 400 Mbps fully differential data path.
  • 145 ps (typ) of pk-pk jitter with PRBS = 223.
  • 1 data pattern at 400 Mbps.
  • Single +3.3 V Supply.
  • Balanced output impedance.
  • Output channel-to-channel skew is 35ps (typ).
  • Differential output voltage (VOD) is 320mV (typ) with 100Ω termination load.
  • LVDS receiver inputs accept LVPECL signals.
  • LVDS input failsafe.
  • Fast propagation delay of 2.8 ns (typ).

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Datasheet preview – DS90LV110AT

Datasheet Details

Part number DS90LV110AT
Manufacturer Texas Instruments
File Size 739.97 KB
Description 1 to 10 LVDS Data/Clock Distributor
Datasheet download datasheet DS90LV110AT Datasheet
Additional preview pages of the DS90LV110AT datasheet.

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Full PDF Text Transcription

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DS90LV110AT www.ti.com SNOSAC2J – AUGUST 2004 – REVISED APRIL 2013 DS90LV110AT 1 to 10 LVDS Data/Clock Distributor with Failsafe Check for Samples: DS90LV110AT FEATURES 1 •2 Low jitter 400 Mbps fully differential data path • 145 ps (typ) of pk-pk jitter with PRBS = 223−1 data pattern at 400 Mbps • Single +3.3 V Supply • Balanced output impedance • Output channel-to-channel skew is 35ps (typ) • Differential output voltage (VOD) is 320mV (typ) with 100Ω termination load. • LVDS receiver inputs accept LVPECL signals • LVDS input failsafe • Fast propagation delay of 2.
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