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DS90UR916Q Datasheet Preview

DS90UR916Q Datasheet

24-bit Color FPD-Link2 Deserializer

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DS90UR916Q
www.ti.com
SNOSB46E – MARCH 2011 – REVISED APRIL 2013
DS90UR916Q 5 - 65 MHz 24-bit Color FPD-Link II Deserializer with Image Enhancement
Check for Samples: DS90UR916Q
FEATURES
1
2 5 – 65 MHz PCLK support (140 Mbps – 1.82
Gbps)
• RGB888 + VS, HS, DE Support
• Image Enhancement - White Balance LUTs and
Adaptive Hi-FRC Dithering
• AC Coupled STP Interconnect Cable up to 10
Meters
• @ Speed Link BIST Mode and Reporting Pin
• I2C Compatible Serial Control Bus
• Power Down Mode Minimizes Power
Dissipation
• 1.8V or 3.3V Compatible LVCMOS I/O Interface
• Automotive Grade Product: AEC-Q100 Grade 2
Qualified
• >8 kV HBM and ISO 10605 ESD Rating
• FAST Random Ddata Lock; No Reference
Clock Required
• Adjustable Input Receiver Equalization
• LOCK (Real Time Link Status) Reporting Pin
• EMI Minimization on Output Parallel Bus
(SSCG)
• Output Slew Control (OS)
• Backward Compatible Mode for Operation with
Older Generation Devices
APPLICATIONS
• Automotive Display for Navigation
• Automotive Display for Entertainment
DESCRIPTION
The DS90UR916Q FPD-Link II deserializer operates
with the DS90UR905Q FPD-Link II serializer to
deliver 24-bit digital video data over a single
differential pair. The DS90UR916Q provides features
designed to enhance image quality at the display.
The high speed serial bus scheme of FPD-Link II
greatly eases system design by eliminating skew
problems between clock and data, reduces the
number of connector pins, reduces the interconnect
size, weight, and cost, and overall eases PCB layout.
In addition, internal DC balanced decoding is used to
support AC-coupled interconnects.
The DS90UR916Q Des (deserializer) recovers the
data (RGB) and control signals and extracts the clock
from the serial stream. The Des locks to the incoming
serial data stream without the use of a training
sequence or special SYNC patterns, and does not
require a reference clock. A link status (LOCK) output
signal is provided. The DS90UR916Q is ideally suited
for 24-bit color applications. White balance lookup
tables and adaptive Hi-FRC dithering provide the user
a cost-effective means to enhance display image
quality.
Serial transmission is optimized with user selectable
receiver equalization. EMI is minimized by the use of
low voltage differential signaling, output slew control,
and the Des may be configured to generate Spread
Spectrum Clock and Data on its parallel outputs.
The DS90UR916Qis offered in a 60-pin WQFN
package. It is specified over the automotive AEC-
Q100 grade 2 temperature range of -40°C to +105°C.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011–2013, Texas Instruments Incorporated




etcTI

DS90UR916Q Datasheet Preview

DS90UR916Q Datasheet

24-bit Color FPD-Link2 Deserializer

No Preview Available !

DS90UR916Q
SNOSB46E – MARCH 2011 – REVISED APRIL 2013
Applications Diagram
VDDIO VDDn
(1.8V or 3.3V) 1.8V
HOST
Graphics
Processor
R[7:0]
G[7:0]
B[7:0]
HS
VS
DE
PCLK
PDB
BISTEN
Optional
SCL
SDA
ID[x]
DOUT+
DOUT-
DS90UR905Q
Serializer
DAP
VDDn VDDIO
1.8V (1.8V or 3.3V)
FPD-Link II
1 Pair / AC Coupled
100 nF
100 nF
100 ohm STP Cable
CMF
CONFIG [1:0]
RFB
VODSEL
DeEmph
Optional
PDB
BISTEN
SCL
SDA
ID[x]
RIN+
RIN-
DS90UR916Q
Deserializer
DAP
R[7:0]
G[7:0]
B[7:0]
HS
VS
DE
PCLK
LOCK
PASS
STRAP pins
not shown
www.ti.com
RGB Display
QVGA to XGA
24-bit or
18-bit dithered
color depth
Block Diagrams
CMF
RIN+
RIN-
Figure 1.
SSCG
24
RGB [7:0]
HS
VS
DE
STRAP INPUT
CONFIG [1:0]
LF_MODE
OS_PCLK/DATA
OSS_SEL
RFB
EQ [3:0]
OSC_SEL [2:0]
SSC [3:0]
MAPSEL [1:0]
BISTEN
PDB
SCL
SCA
ID[x]
Timing and
Control
Error
Detector
Clock and
Data
Recovery
DS90UR916Q ± DESERIALIZER
Figure 2.
PASS
PCLK
LOCK
STRAP INPUT
OP_LOW
2 Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: DS90UR916Q


Part Number DS90UR916Q
Description 24-bit Color FPD-Link2 Deserializer
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