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DS92LV2422 Datasheet Preview

DS92LV2422 Datasheet

Link-II Serializer/Deserializer

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DS92LV2421, DS92LV2422
SNLS321C – MAY 2010 – REVISED MAY 2016
DS92LV242x 10-MHz to 75-MHz, 24-Bit Channel Link II Serializer And Deserializer
1 Features
1 24-Bit Data, 3-Bit Control, 10- to 75-MHz Clock
• AC-Coupled STP Interconnect Cable up to 10 m
• Integrated Terminations on Serializer and
Deserializer
• At-Speed Link BIST Mode and Reporting Pin
• Optional I2C-Compatible Serial Control Bus
• Power-Down Mode Minimizes Power Dissipation
• 1.8-V or 3.3-V Compatible LVCMOS I/O Interface
• –40° to 85°C Temperature Range
• >8-kV HBM
• Serializer (DS92LV2421)
– Data Scrambler for Reduced EMI
– DC-Balance Encoder for AC Coupling
– Selectable Output VOD and Adjustable
De-emphasis
• Deserializer (DS92LV2422)
– Fast Random Data Lock; No Reference Clock
Required
– Adjustable Input Receiver Equalization
– LOCK (Real-Time Link Status) Reporting Pin
– EMI Minimization on Output Parallel Bus
(SSCG)
– Output Slew Control (OS)
2 Applications
• Embedded Videos and Displays
• Medical Imaging and Factory Automation
• Office Automation (Printers and Scanners)
• Security and Video Surveillance
• General-Purpose Data Communication
3 Description
The DS92LV242x chipset translates a parallel 24–bit
LVCMOS data interface into a single high-speed CML
serial interface with embedded clock information. This
single serial stream eliminates skew issues between
clock and data, reduces connector size, and reduces
interconnect cost for transferring a 24-bit or less bus
over FR-4 printed-circuit board backplanes and
balanced cables. In addition, the DS92LV242x
chipset also features a 3-bit control bus for slow
speed signals. This allows for video and display
applications with up to 24 bits per pixel (RGB).
Programmable transmit de-emphasis, receive
equalization, on-chip scrambling, and DC balancing
enables longer distance transmission over lossy
cables and backplanes. The DS92LV2422
automatically locks to incoming data without an
external reference clock or special sync patterns,
providing easy plug-and-go operation. EMI is
minimized by the use of low voltage differential
signaling, receiver drive strength control, and spread
spectrum clocking capability.
The DS92LV242x chipset is programmable though an
I2C interface as well as through pins. A built-in, at-
speed BIST feature validates link integrity and may
be used for system diagnostics. The DS92LV2421 is
offered in a 48-pin WQFN, and the DS92LV2422 is
offered in a 60-pin WQFN package. Both devices
operate over the full industrial temperature range of
–40°C to 85°C.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
DS92LV2421
WQFN (48)
7.00 mm × 7.00 mm
DS92LV2422
WQFN (60)
9.00 mm × 9.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Block Diagram
VDDIO VDDn
(1.8V or 3.3V) 1.8V
VDDn VDDIO
1.8V (1.8V or 3.3V)
Graphic
Processor
OR
Video
Imager
OR
ASIC/FPGA
DI[7:0]
DI[15:8]
DI[23:16]
CI1
CI2
CI3
CLKIN
PDB
BISTEN
Optional
SCL
SDA
ID[x]
DOUT+
DOUT-
DS92LV2421
Serializer
DAP
Channel Link II
1 Pair / AC Coupled
100 nF
100 nF
100 ohm STP Cable
CMF
RFB
VODSEL
DeEmph
Optional
PDB
BISTEN
SCL
SDA
ID[x]
RIN+
RIN-
DS92LV2422
Deserializer
DAP
DO[7:0]
DO[15:8]
DO[23:16]
CO1
CO2
CO3
CLKOUT
LOCK
PASS
STRAP pins
not shown
24-bit RGB
Display
OR
ASIC/FPGA
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.




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DS92LV2422 Datasheet Preview

DS92LV2422 Datasheet

Link-II Serializer/Deserializer

No Preview Available !

DS92LV2421, DS92LV2422
SNLS321C – MAY 2010 – REVISED MAY 2016
www.ti.com
Table of Contents
1 Features .................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions ......................... 4
6 Specifications....................................................... 10
6.1 Absolute Maximum Ratings .................................... 10
6.2 ESD Ratings............................................................ 10
6.3 Recommended Operating Conditions..................... 10
6.4 Thermal Information ................................................ 11
6.5 Electrical Characteristics – Serializer DC ............... 11
6.6 Electrical Characteristics – Deserializer DC ........... 12
6.7 Electrical Characteristics – DC and AC Serial Control
Bus ........................................................................... 13
6.8 Timing Requirements – DC and AC Serial Control
Bus ........................................................................... 13
6.9 Timing Requirements – Serializer for CLKIN.......... 13
6.10 Timing Requirements – Serial Control Bus........... 14
6.11 Switching Characteristics – Serializer................... 14
6.12 Switching Characteristics – Deserializer............... 15
6.13 Typical Characteristics .......................................... 21
7 Detailed Description ............................................ 22
7.1 Overview ................................................................. 22
7.2 Functional Block Diagrams ..................................... 22
7.3 Feature Description................................................. 23
7.4 Device Functional Modes........................................ 37
7.5 Register Maps ......................................................... 38
8 Application and Implementation ........................ 41
8.1 Application Information............................................ 41
8.2 Typical Applications ................................................ 42
9 Power Supply Recommendations...................... 46
9.1 Power-Up Requirements and PDB Pin ................... 46
10 Layout................................................................... 47
10.1 Layout Guidelines ................................................. 47
10.2 Layout Example .................................................... 49
11 Device and Documentation Support ................. 51
11.1 Device Support...................................................... 51
11.2 Documentation Support ........................................ 51
11.3 Related Links ........................................................ 51
11.4 Community Resource............................................ 51
11.5 Trademarks ........................................................... 51
11.6 Electrostatic Discharge Caution ............................ 51
11.7 Glossary ................................................................ 52
12 Mechanical, Packaging, and Orderable
Information ........................................................... 52
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (April 2013) to Revision C
Page
• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
• Updated thermal characteristic values based on latest simulation data ............................................................................. 11
• Changed deserializer LVCMOS DC and supply current specification test conditions based on latest production tests .... 12
• Changed IOL test condition for VOL at VDDIO = 3.3 V to 3 mA ............................................................................................... 12
• Changed max value of Deserializer VOL to 0.45 V .............................................................................................................. 12
• Changed test condition parameter for VOL Serial Control Characteristic ............................................................................ 13
• Changed RPU = 10 kcondition for the Serial Control Bus Characteristics of tR and tF ................................................... 13
• Added notes for serializer and deserializer switching characteristics verified by characterization ...................................... 14
• Added corresponding pins for deserializer tCLH and tCHL parameter..................................................................................... 15
• Added test condition to tDD deserializer parameter ............................................................................................................. 15
• Changed corrected units for deserializer lock time and delay parameter ........................................................................... 15
• Added serial stream and video control signal filter waveform to Feature Description ........................................................ 23
• Changed "NA" and "Disable" term in Table 5 and Table 6 to "Off" ..................................................................................... 28
• Changed output states to correct values based on OSS_SEL and PDB configuration in Table 7 ..................................... 29
• Added details for Deserializer Map Select strap pin configuration ...................................................................................... 33
• Added clarification on the state of deserializer outputs during BIST mode operation.......................................................... 33
• Added statement to set input to low when entering BIST mode with DS90C241 or DS90UR241 ..................................... 33
• Added note that ID[X] cannot be tied to VSS, as only four device addresses are supported ............................................. 35
• Added RID tolerance and tablenote that RID 0 Ω to set ID[X] ......................................................................................... 35
• Changed statement that CONFIG settings can also by programmed via register .............................................................. 37
2
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Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: DS92LV2421 DS92LV2422


Part Number DS92LV2422
Description Link-II Serializer/Deserializer
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