Datasheet4U Logo Datasheet4U.com

LMK04228 - Clock Jitter Cleaner

General Description

The LMK04228 device is the performance clock conditioner JESD204B support.

The 14 clock outputs from PLL2 can be configured to drive seven JESD204B converters or other logic devices using device and SYSREF clocks.

SYSREF can be provided using both DC and AC coupling.

Key Features

  • 1 JEDEC JESD204B Support.
  • Ultra-Low RMS Jitter.
  • 156 fs RMS Jitter (12 kHz to 20 MHz).
  • 245 fs RMS Jitter (100 Hz to 20 MHz).
  • 162.5 dBc/Hz Noise Floor at 245.76 MHz.
  • Up to 14 Differential Device Clocks from PLL2.
  • Up to 7 SYSREF Clocks.
  • Maximum Clock Output Frequency: 1.25 GHz.
  • LVPECL, LVDS Programmable Outputs From PLL2.
  • Buffered VCXO or Crystal Output From PLL1.
  • LVPECL, LVDS, 2xLVCMOS Progr.

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
LMK042 MULTILAYER CERAMIC CAPACITORS Taiyo Yuden
LMK04000 Low-Noise Clock Jitter Cleaner National Semiconductor
LMK04031B Precision Clock Conditioners Low-Noise Clock Jitter Cleaner National Semiconductor Corporation
LMK04800 Low-Noise Clock Jitter Cleaner National Semiconductor
LMK01000 (LMK01000 - LMK01020) 1.6 GHz High Performance Clock Buffer National Semiconductor

Other Datasheets by Texas Instruments

Part Number Description
LMK04208 Low-Noise Clock Jitter Cleaner
LMK04000 Family Low-Noise Clock Jitter Cleaner
LMK04001 Family Low-Noise Clock Jitter Cleaner
LMK04002 Family Low-Noise Clock Jitter Cleaner
LMK04010 Family Low-Noise Clock Jitter Cleaner

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
Product Folder Order Now Technical Documents Tools & Software Support & Community LMK04228 SNAS689A – OCTOBER 2017 – REVISED JULY 2019 LMK04228 Ultra-Low Noise, JESD204B-Compliant Clock Jitter Cleaner With Dual-Loop PLLs 1 Features •1 JEDEC JESD204B Support • Ultra-Low RMS Jitter – 156 fs RMS Jitter (12 kHz to 20 MHz) – 245 fs RMS Jitter (100 Hz to 20 MHz) – –162.5 dBc/Hz Noise Floor at 245.76 MHz • Up to 14 Differential Device Clocks from PLL2 – Up to 7 SYSREF Clocks – Maximum Clock Output Frequency: 1.