LMK04208 Datasheet | Texas Instruments

Features - 1 Ultra-Low RMS Jitter Performance - 111 fs, RMS Jitter (12 k Hz to 20 MHz) - 123 fs, RMS Jitter (100 Hz to 20 MHz) - Dual Loop PLLatinum™ PLL Architecture - PLL1 - Integrated Low-Noise Crystal Oscillator Circuit - Holdover Mode when Input Clocks are Lost - Automatic or Manual Triggering/Recovery - PLL2 - Normalized PLL Noise Floor of - 227 d Bc/Hz - Phase Detector Rate of Up to 155 MHz - OSCin Frequency-Doubler - Integrated Low-Noise VCO or External VCO Mode - Two Redundant Input Clocks with LOS - Automatic and Manual Switch-Over Modes - 50 % Duty Cycle Output Divides, 1 to 1045 (Even and Odd) - 6 LVPECL, LVDS, or LVCMOS Programmable Outputs - Digital Delay: Fixed or Dynamically Adjustable - 25 ps Step Analog Delay Control - 7 Differential Outputs, Up to 14 Single-Ended - Up to 6 VCXO/Crystal Buffered Outputs - Clock Rates of Up to 1536 MHz - 0-Delay Mode - Three Default Clock Outputs at Power Up - Multi-Mode: Dual PLL, Single PLL, and Clock Distribution - Industrial Temperature Range: - 40°C to +85°C - 3.15-V to 3.45-V Operation - 64-Pin WQFN Package (9.0 × 9.0 × 0.8 mm) 2 Applications - Data Converter Clocking - Wireless Infrastructure - Networking, SONET/SDH, DSLAM - Medical, Video, Military, Aerospace - Test and...