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LMK04228 Datasheet Clock Jitter Cleaner

Manufacturer: Texas Instruments

Overview: Product Folder Order Now Technical Documents Tools & Software Support & munity LMK04228 SNAS689A – OCTOBER 2017 – REVISED JULY 2019 LMK04228 Ultra-Low Noise, JESD204B-pliant Clock Jitter Cleaner With Dual-Loop PLLs.

General Description

The LMK04228 device is the performance clock conditioner JESD204B support.

industry's high with JEDEC The 14 clock outputs from PLL2 can be configured to drive seven JESD204B converters or other logic devices using device and SYSREF clocks.

SYSREF can be provided using both DC and AC coupling.

Key Features

  • 1 JEDEC JESD204B Support.
  • Ultra-Low RMS Jitter.
  • 156 fs RMS Jitter (12 kHz to 20 MHz).
  • 245 fs RMS Jitter (100 Hz to 20 MHz).
  • 162.5 dBc/Hz Noise Floor at 245.76 MHz.
  • Up to 14 Differential Device Clocks from PLL2.
  • Up to 7 SYSREF Clocks.
  • Maximum Clock Output Frequency: 1.25 GHz.
  • LVPECL, LVDS Programmable Outputs From PLL2.
  • Buffered VCXO or Crystal Output From PLL1.
  • LVPECL, LVDS, 2xLVCMOS Progr.

More Datasheets from Texas Instruments

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