LMK04616 cleaner equivalent, ultra-low noise and low power jesd204b compliant clock jitter cleaner.
*1 Dual-loop PLL architecture
* Ultra low noise (10 kHz to 20 MHz):
– 48-fs RMS jitter at 1966.08 MHz
– 50-fs RMS jitter at 983.04.
* Wireless infrastructure like LTE-BTS, small cells, remote radio units (RRU)
* Data converter and integrated tr.
The LMK0461x device family is the industry’s highest performance and lowest power jitter cleaner with JESD204B support. The 16 clock outputs can be configured to drive eight JESD204B converters or other logic devices using device and SYSREF clocks. T.
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