* 1 One Digital Phase-Locked Loop (DPLL) With:
* Hitless Switching: ±50-ps Phase Transient
* Programmable Loop Bandwidth With Fastlock
* Standards-Compliant Synchronization and Holdover Using a Low-Cost TCXO/OCXO
* Two Analog Phase-Locked Loops (APLLs) With Ind
LMK05318
2.58 MB
Ultra-low jitter network synchronizer clock.
Product Folder Order Now Technical Documents Tools & Software Support & Community LMK05318 SNAS771A DECEMBER 2018 REVISED DEC.
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