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LMK05318 - Ultra-Low Jitter Network Synchronizer Clock

General Description

The LMK05318 is a high-performance network synchronizer clock device that provides jitter cleaning, clock generation, advanced clock monitoring, and superior hitless switching performance to meet the stringent timing requirements of communications infrastructure and industrial applications.

Key Features

  • 1 One Digital Phase-Locked Loop (DPLL) With:.
  • Hitless Switching: ±50-ps Phase Transient.
  • Programmable Loop Bandwidth With Fastlock.
  • Standards-Compliant Synchronization and Holdover Using a Low-Cost TCXO/OCXO.
  • Two Analog Phase-Locked Loops (APLLs) With Industry-Leading Jitter Performance:.
  • 50-fs RMS Jitter at 312.5 MHz (APLL1).
  • 125-fs RMS Jitter at 155.52 MHz (APLL2).
  • Two Reference Clock Inputs.
  • Priority-Based Input.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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Product Folder Order Now Technical Documents Tools & Software Support & Community LMK05318 SNAS771A – DECEMBER 2018 – REVISED DECEMBER 2018 LMK05318 Ultra-Low Jitter Network Synchronizer Clock With Two Frequency Domains 1 Features •1 One Digital Phase-Locked Loop (DPLL) With: – Hitless Switching: ±50-ps Phase Transient – Programmable Loop Bandwidth With Fastlock – Standards-Compliant Synchronization and Holdover Using a Low-Cost TCXO/OCXO • Two Analog Phase-Locked Loops (APLLs) With Industry-Leading Jitter Performance: – 50-fs RMS Jitter at 312.5 MHz (APLL1) – 125-fs RMS Jitter at 155.