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LMK05318 Datasheet Preview

LMK05318 Datasheet

Ultra-Low Jitter Network Synchronizer Clock

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LMK05318
SNAS771A – DECEMBER 2018 – REVISED DECEMBER 2018
LMK05318 Ultra-Low Jitter Network Synchronizer Clock With Two Frequency Domains
1 Features
1 One Digital Phase-Locked Loop (DPLL) With:
– Hitless Switching: ±50-ps Phase Transient
– Programmable Loop Bandwidth With Fastlock
– Standards-Compliant Synchronization and
Holdover Using a Low-Cost TCXO/OCXO
• Two Analog Phase-Locked Loops (APLLs) With
Industry-Leading Jitter Performance:
– 50-fs RMS Jitter at 312.5 MHz (APLL1)
– 125-fs RMS Jitter at 155.52 MHz (APLL2)
• Two Reference Clock Inputs
– Priority-Based Input Selection
– Digital Holdover on Loss of Reference
• Eight Clock Outputs With Programmable Drivers
– Up to Six Different Output Frequencies
– AC-LVDS, AC-CML, AC-LVPECL, HCSL, and
1.8-V LVCMOS Output Formats
• EEPROM / ROM for Custom Clocks on Power-Up
• Flexible Configuration Options
– 1 Hz (1 PPS) to 800 MHz on Input and Output
– XO/TCXO/OCXO Input: 10 to 100 MHz
– DCO Mode: < 0.001 ppb/Step for Precise
Clock Steering (IEEE 1588 PTP Slave)
– Advanced Clock Monitoring and Status
– I2C or SPI Interface
• PSNR: –83 dBc (50-mVpp Noise on 3.3-V Supply)
• 3.3-V Supply With 1.8-V, 2.5-V, or 3.3-V Outputs
• Industrial Temperature Range: –40°C to +85°C
2 Applications
• SyncE (G.8262), SONET/SDH (Stratum 3/3E,
G.813, GR-1244, GR-253), IEEE 1588 PTP Slave
Clock, or Optical Transport Network (G.709)
• 400G Line Cards, Fabric Cards for Ethernet
Switches and Routers
• Wireless Base Station (BTS), Wireless Backhaul
• Test and Measurement, Medical Imaging
• Jitter Cleaning, Wander Attenuation, and
Reference Clock Generation for 56G/112G PAM-4
PHYs, ASICs, FPGAs, SoCs, and Processors
3 Description
The LMK05318 is a high-performance network
synchronizer clock device that provides jitter cleaning,
clock generation, advanced clock monitoring, and
superior hitless switching performance to meet the
stringent timing requirements of communications
infrastructure and industrial applications. The ultra-
low jitter and high power supply noise rejection
(PSNR) of the device can reduce bit error rates
(BER) in high-speed serial links.
The device can generate output clocks with 50-fs
RMS jitter using TI's proprietary Bulk Acoustic Wave
(BAW) VCO technology, independent of the jitter and
frequency of the XO and reference inputs.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
LMK05318
VQFN (48)
7.00 mm × 7.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Block Diagram
VDD
VDDO
3.3 V 1.8 / 2.5 / 3.3 V
Differential
or LVCMOS
PRIREF
SECREF
XO/
TCXO/
OCXO
I2C/SPI
LOGIC I/Os
STATUS
Power Conditioning
LMK05318
Ultra-Low Jitter
Network Synchronizer Clock
÷R
Hitless
Switching
×1, ×2
DPLL
DCO
÷
APLL1
VCO1
÷
Registers
EEPROM,
ROM
Device Control
and Status
APLL2
÷
VCO2 ÷
Output
Muxes
÷OD
÷OD
÷OD
÷OD
÷OD
÷OD
OUT0
OUT1
OUT2
OUT3
Differential
or HCSL
OUT4
OUT5
OUT6
OUT7
Differential,
HCSL, or
1.8-V LVCMOS
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.




etcTI

LMK05318 Datasheet Preview

LMK05318 Datasheet

Ultra-Low Jitter Network Synchronizer Clock

No Preview Available !

LMK05318
SNAS771A – DECEMBER 2018 – REVISED DECEMBER 2018
www.ti.com
Table of Contents
1 Features .................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Description (continued)......................................... 3
6 Pin Configuration and Functions ......................... 4
6.1 Device Start-Up Modes ............................................. 7
7 Specifications......................................................... 8
7.1 Absolute Maximum Ratings ...................................... 8
7.2 ESD Ratings.............................................................. 8
7.3 Recommended Operating Conditions....................... 8
7.4 Thermal Information: 4-Layer JEDEC Standard
PCB............................................................................ 9
7.5 Thermal Information: 10-Layer Custom PCB............ 9
7.6 Electrical Characteristics........................................... 9
7.7 Timing Diagrams ..................................................... 15
7.8 Typical Characteristics ............................................ 17
8 Parameter Measurement Information ................ 19
8.1 Output Clock Test Configurations ........................... 19
9 Detailed Description ............................................ 21
9.1 Overview ................................................................. 21
9.2 Functional Block Diagram ....................................... 22
9.3 Feature Description................................................. 26
9.4 Device Functional Modes........................................ 51
9.5 Programming .......................................................... 57
10 Application and Implementation........................ 64
10.1 Application Information.......................................... 64
10.2 Typical Application ................................................ 67
10.3 Do's and Don'ts ..................................................... 73
11 Power Supply Recommendations ..................... 74
11.1 Power Supply Bypassing ...................................... 74
11.2 Device Current and Power Consumption.............. 75
12 Layout................................................................... 76
12.1 Layout Guidelines ................................................. 76
12.2 Layout Example .................................................... 76
12.3 Thermal Reliability................................................. 77
13 Device and Documentation Support ................. 78
13.1 Device Support...................................................... 78
13.2 Receiving Notification of Documentation Updates 78
13.3 Community Resources.......................................... 78
13.4 Trademarks ........................................................... 78
13.5 Electrostatic Discharge Caution ............................ 78
13.6 Glossary ................................................................ 78
14 Mechanical, Packaging, and Orderable
Information ........................................................... 78
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (June 2018) to Revision A
Page
• Changed device status from Advanced Information to Production Data................................................................................ 1
2 Submit Documentation Feedback
Product Folder Links: LMK05318
Copyright © 2018, Texas Instruments Incorporated


Part Number LMK05318
Description Ultra-Low Jitter Network Synchronizer Clock
Maker etcTI
Total Page 30 Pages
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