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PGA117 - Zero-Drift Programmable Gain Amplifier

This page provides the datasheet information for the PGA117, a member of the PGA112 Zero-Drift Programmable Gain Amplifier family.

Description

The PGA112 and PGA113 devices (binary and scope gains) offer two analog inputs, a three-pin SPI interface, and software shutdown in a 10-pin, VSSOP package.

Features

  • 1 Rail-to-Rail Input and Output.
  • Offset: 25 μV (Typical), 100 μV (Maximum).
  • Zerø Drift: 0.35 μV/°C (Typical), 1.2 μV/°C (Maximum).
  • Low Noise: 12 nV/√Hz.
  • Input Offset Current: ±5 nA Maximum (25°C).
  • Gain Error: 0.1% Maximum (G ≤ 32), 0.3% Maximum (G > 32).
  • Binary Gains: 1, 2, 4, 8, 16, 32, 64, 128 (PGA112, PGA116).
  • Scope Gains: 1, 2, 5, 10, 20, 50, 100, 200 (PGA113, PGA117).
  • Gain Switching Time: 200 ns.
  • 2 Cha.

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Datasheet preview – PGA117

Datasheet Details

Part number PGA117
Manufacturer Texas Instruments
File Size 2.20 MB
Description Zero-Drift Programmable Gain Amplifier
Datasheet download datasheet PGA117 Datasheet
Additional preview pages of the PGA117 datasheet.

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Full PDF Text Transcription

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Product Folder Sample & Buy Technical Documents Tools & Software Support & Community Reference Design PGA112, PGA113, PGA116, PGA117 SBOS424C – MARCH 2008 – REVISED NOVEMBER 2015 PGA11x Zerø-Drift Programmable Gain Amplifier With Mux 1 Features •1 Rail-to-Rail Input and Output • Offset: 25 μV (Typical), 100 μV (Maximum) • Zerø Drift: 0.35 μV/°C (Typical), 1.2 μV/°C (Maximum) • Low Noise: 12 nV/√Hz • Input Offset Current: ±5 nA Maximum (25°C) • Gain Error: 0.1% Maximum (G ≤ 32), 0.
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