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SCANPSC100F Key Features

  • 23 patible with IEEE Std. 1149.1 (JTAG) Test Access Port and Boundary Scan Architecture
  • Supported by Texas Instruments SCAN Ease (Embedded Application Software Enabler) Software
  • Uses Generic, Asynchronous Processor Interface; patible with a Wide Range of Processors and PCLK Frequencies
  • Directly Supports Up to Two 1149.1 Scan Chains
  • 16-bit Serial Signature paction (SSC) at the Test Data In (TDI) Port
  • Automatically Produces Pseudo-Random Patterns at the Test Data Out (TDO) Port
  • Fabricated on FACT™ 1.5 μm CMOS Process
  • Supports 1149.1 Test Clock (TCK) Frequencies up to 25 MHz
  • TTL-patible Inputs; Full-Swing CMOS Outputs with 24 mA Source/Sink Capability
  • Standard Microcircuit Drawing (SMD) 5962-9475001

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SCANPSC100F Description

The SCANPSC100F is designed to interface a generic parallel processor bus to a serial scan test bus. It is useful in improving scan throughput when applying serial vectors to system test circuitry and reduces the software overhead that is associated with applying serial patterns with a parallel processor. The 'PSC100F operates by serializing data from the parallel bus for shifting through the chain of 1149.1 pliant...