SN65LVDS180-EP Datasheet | Texas Instruments

FEATURES - Controlled Baseline - One Assembly/Test Site, One Fabrication Site - Enhanced Diminishing Manufacturing Sources (DMS) Support - Enhanced Product-Change Notification - Qualification Pedigree (1) - Meet or Exceed the Requirements of ANSI TIA/EIA-644-1995 Standard - Signaling Rates up to 400 Mbps - Bus-Terminal ESD Exceeds 12 k V - Operates From a Single 3.3-V Supply - Low-Voltage Differential Signaling With Typical Output Voltages of 350 m V and a 100-Ω Load - Propagation Delay Times - Driver: 1.7 ns Typ - Receiver: 3.7 ns Typ - Power Dissipation at 200 MHz - Driver: 25 m W Typical - Receiver: 60 m W Typical - LVTTL Input Levels Are 5-V Tolerant - Receiver Maintains High Input Impedance With VCC < 1.5 V - Receiver Has Open-Circuit Fail Safe SN65LVDS179 D OR DGK PACKAGE (TOP VIEW) VCC 1 R2 D3 GND 4 8A 7B 6Z 5Y SN65LVDS180 D OR PW PACKAGE (TOP VIEW) NC 1 R2 RE 3 DE 4 D5 GND 6 GND 7 14 VCC 13 VCC 12 A 11 B 10 Z 9Y 8 NC SN65LVDS050 D OR PW PACKAGE (TOP VIEW) 1B 1 1A 2 1R 3 RE 4 2R 5 2A 6 2B 7 GND 8 16 VCC 15 1D 14 1Y 13 1Z 12 DE 11 2Z 10 2Y 9 2D 3 D 2...