SN65LVDS3486
Features
- 1 Meet or Exceed the Requirements of ANSI TIA/EIA-644 Standard
- Operate With a Single 3.3-V Supply
- Designed for Signaling Rates of up to 150 Mbps
(See )
- Differential Input Thresholds ±100 m V Max
- Typical Propagation Delay Time of 2.1 ns
- Power Dissipation 60 m W Typical Per Receiver at
Maximum Data Rate
- Bus-Terminal ESD Protection Exceeds 8 k V
- Low-Voltage TTL (LVTTL) Logic Output Levels
- Pin patible With AM26LS32, MC3486, and
μA9637
- Open-Circuit Fail-Safe
- Cold Sparing for Space and High-Reliability
Applications Requiring Redundancy
2 Applications
- Wireless Infrastructure
- Tele Infrastructure
- Printer
3 Description
The SN55LVDS32, SN65LVDS32, SN65LVDS3486, and SN65LVDS9637 devices are differential line receivers that implement the electrical characteristics of low-voltage differential signaling (LVDS). This signaling technique lowers the output voltage levels of 5-V differential standard levels (such as EIA/TIA422B) to reduce the power, increase the...
