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SN65LVP19 - 2.5-V/3.3-V OSCILLATOR GAIN STAGE/BUFFERS

Download the SN65LVP19 datasheet PDF (SN65LVDS18 included). The manufacturer datasheet provides complete specifications, pinout details, electrical characteristics, and typical applications for 2.5-v/3.3-v oscillator gain stage/buffers.

Description

These four devices are high frequency oscillator gain stages supporting both LVPECL or LVDS on the high gain outputs in 3.3-V or 2.5-V systems.

Additionally, provides the option of both single-ended input (PECL levels on the SN65LVx18) and fully differential inputs on the SN65LVx19.

Features

  • Low-Voltage PECL Input and Low-Voltage PECL or LVDS Outputs.
  • Clock Rates to 1 GHz.
  • 250-ps Output Transition Times.
  • 0.12 ps Typical Intrinsic Phase Jitter.
  • Less than 630 ps Propagation Delay Times.
  • 2.5-V or 3.3-V Supply Operation.
  • 2-mm x 2-mm Small-Outline No-Lead Package.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (SN65LVDS18-etcTI.pdf) that lists specifications for multiple related part numbers.

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Full PDF Text Transcription

Click to expand full text
www.ti.com SN65LVDS18, SN65LVP18 SN65LVDS19, SN65LVP19 SLLS624B – SEPTEMBER 2004 – REVISED NOVEMBER 2005 2.5-V/3.3-V OSCILLATOR GAIN STAGE/BUFFERS FEATURES • Low-Voltage PECL Input and Low-Voltage PECL or LVDS Outputs • Clock Rates to 1 GHz – 250-ps Output Transition Times – 0.12 ps Typical Intrinsic Phase Jitter – Less than 630 ps Propagation Delay Times • 2.5-V or 3.3-V Supply Operation • 2-mm x 2-mm Small-Outline No-Lead Package APPLICATIONS • PECL-to-LVDS Translation • Clock Signal Amplification DESCRIPTION These four devices are high frequency oscillator gain stages supporting both LVPECL or LVDS on the high gain outputs in 3.3-V or 2.5-V systems.
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