SN74AHC125Q Datasheet | Texas Instruments

D Q Devices Meet Automotive Performance Requirements D Customer-Specific Configuration Control Can Be Supported Along With Major-Change Approval D EPIC™ (Enhanced-Performance Implanted CMOS) Process D Operating Range 2-V to 5.5-V VCC D Latch-Up Performance Exceeds 250 m A Per JESD 17 SN74AHC125Q QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS SGDS015 - FEBRUARY 2002 D OR PW PACKAGE (TOP VIEW) 1OE 1A 1Y 2OE 2A 2Y 1 2 3 4 5 6 7 14 VCC 13 4OE 12 4A 11 4Y 10 3OE 9 3A 8 3Y description The SN74AHC125Q is a quadruple bus buffer gate featuring independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is high. When OE is low, the respective gate passes the data from the A input to its Y output. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. ORDERING INFORMATION PACKAGE† ORDERABLE PART NUMBER TOP-SIDE MARKING - 40°C to 125°C SOIC - D TSSOP - PW Tape and reel Tape and reel SN74AHC125QDR SN74AHC125QPWR AHC125Q...