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SN74AHCT138-EP Datasheet Preview

SN74AHCT138-EP Datasheet

3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS

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SN74AHCT138-EP
3-LINE TO 8-LINE DECODER/DEMULTIPLEXER
D Controlled Baseline
– One Assembly/Test Site, One Fabrication
Site
D Extended Temperature Performance of
–55°C to 125°C
D Enhanced Diminishing Manufacturing
Sources (DMS) Support
D Enhanced Product-Change Notification
D Qualification Pedigree
D EPIC(Enhanced-Performance Implanted
CMOS) Process
D Inputs Are TTL-Voltage Compatible
D Designed Specifically for High-Speed
Memory Decoders and Data-Transmission
Systems
Component qualification in accordance with JEDEC and industry
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, Highly
Accelerated Stress Test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life. Such qualification
testing should not be viewed as justifying use of this component
beyond specified performance and environmental limits.
SCLS491 – JUNE 2003
D Incorporates Three Enable Inputs to
Simplify Cascading and/or Data Reception
D Latch-Up Performance Exceeds 250 mA Per
JESD 17
D ESD Protection Exceeds 2000 V Per
MIL-STD-833, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D OR PW PACKAGE
(TOP VIEW)
A1
B2
C3
G2A 4
G2B 5
G1 6
Y7 7
GND 8
16 VCC
15 Y0
14 Y1
13 Y2
12 Y3
11 Y4
10 Y5
9 Y6
description/ordering information
The SN74AHCT138 3-line to 8-line decoder/demultiplexer is designed to be used in high-performance
memory-decoding and data-routing applications that require very short propagation-delay times. In
high-performance memory systems, this decoder can be used to minimize the effects of system decoding.
When employed with high-speed memories utilizing a fast enable circuit, the delay times of this decoder and
the enable time of the memory usually are less than the typical access time of the memory. This means that
the effective system delay introduced by the decoder is negligible.
The conditions at the binary-select inputs and the three enable inputs select one of eight output lines. Two
active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding.
A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one
inverter. An enable input can be used as a data input for demultiplexing applications.
ORDERING INFORMATION
TA
PACKAGE‡
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
SOIC – D
–55°C to 125°C
TSSOP – PW
Tape and reel
Tape and reel
SN74AHCT138MDREP
AHCT138MEP
SN74AHCT138MPWREP AT138EP
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 2003, Texas Instruments Incorporated
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
1




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SN74AHCT138-EP Datasheet Preview

SN74AHCT138-EP Datasheet

3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS

No Preview Available !

SN74AHCT138-EP
3-LINE TO 8-LINE DECODER/DEMULTIPLEXER
SCLS491 JUNE 2003
FUNCTION TABLE
ENABLE INPUTS
SELECT INPUTS
OUTPUTS
G1 G2A G2B C
B
A
Y0 Y1 Y2 Y3 Y4 Y5 Y6
X
H
X
X
X
X
H
H
H
H
H
H
H
X
X
H
X
X
X
H
H
H
H
H
H
H
L
X
X
X
X
X
H
H
H
H
H
H
H
H
L
L
L
L
L
L
H
H
H
H
H
H
H
L
L
L
L
H
H
L
H
H
H
H
H
H
L
L
L
H
L
H
H
L
H
H
H
H
H
L
L
L
H
H
H
H
H
L
H
H
H
H
L
L
H
L
L
H
H
H
H
L
H
H
H
L
L
H
L
H
H
H
H
H
H
L
H
H
L
L
H
H
L
H
H
H
H
H
H
L
H
L
L
H
H
H
H
H
H
H
H
H
H
logic symbols (alternatives)
1
A
2
B
3
C
6
G1
4
G2A
5
G2B
BIN/OCT
1
0
2
1
4
2
3
&
4
EN
5
6
7
15
Y0
14
Y1
13
Y2
12
Y3
11
Y4
10
Y5
9
Y6
7
Y7
1
A
2
B
3
C
6
G1
4
G2A
5
G2B
DMUX
0
0
G
0
7
1
2
2
3
&
4
5
6
7
These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Y7
H
H
H
H
H
H
H
H
H
H
L
15
Y0
14
Y1
13
Y2
12
Y3
11
Y4
10
Y5
9
Y6
7
Y7
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265


Part Number SN74AHCT138-EP
Description 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
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