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SN74AUP1G79 Datasheet Preview

SN74AUP1G79 Datasheet

Low-Power Single Positive-Edge-Triggered D-Type Flip-Flop

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SN74AUP1G79
SCES592I – JULY 2004 – REVISED SEPTEMBER 2017
SN74AUP1G79 Low-Power Single Positive-Edge-Triggered D-Type Flip-Flop
1 Features
1 Available in the Texas Instruments NanoStar™
Package
• Low Static-Power Consumption:
ICC = 0.9 µA Maximum
• Low Dynamic-Power Consumption:
Cpd = 3 pF Typical at 3.3 V
• Low Input Capacitance:
Ci = 1.5 pF Typical
• Low Noise: Overshoot and Undershoot
< 10% of VCC
• Ioff Supports Partial Power-Down-Mode Operation
• Input Hysteresis Allows Slow Input Transition and
Better Switching Noise Immunity at the Input
(Vhys = 250 mV Typical at 3.3 V)
• Wide Operating VCC Range of 0.8 V to 3.6 V
• Optimized for 3.3-V Operation
• 3.6-V I/O Tolerant to Support Mixed-Mode Signal
Operation
• tpd = 4 ns Maximum at 3.3 V
• Suitable for Point-to-Point Applications
• Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
• ESD Performance Tested Per JESD 22
– 2000-V Human-Body Model
(A114-B, Class II)
– 1000-V Charged-Device Model (C101)
2 Applications
• Barcode Scanner
• Cable Solutions
• E-Book
• Embedded PC
• Field Transmitter: Temperature or Pressure
Sensor
• Fingerprint Biometrics
• HVAC: Heating, Ventilating, and Air Conditioning
• Network-Attached Storage (NAS)
• Server Motherboard and PSU
• Software Defined Radio (SDR)
• TV: High-Definition (HDTV), LCD, and Digital
• Video Communications System
• Wireless Data Access Card, Headset, Keyboard,
Mouse, and LAN Card
3 Description
The AUP family is TI's premier solution to the
industry's low-power needs in battery-powered
portable applications. This family assures a very-low
static and dynamic power consumption across the
entire VCC range of 0.8 V to 3.6 V, thus resulting in an
increased battery life. The AUP devices also maintain
excellent signal integrity.
The SN74AUP1G79 is a single positive-edge-
triggered D-type flip-flop. When data at the data (D)
input meets the setup-time requirement, the data is
transferred to the Q output on the positive-going edge
of the clock pulse. Clock triggering occurs at a
voltage level and is not directly related to the rise
time of the clock pulse. Following the hold-time
interval, data at the D input can be changed without
affecting the levels at the outputs.
NanoStar™ package technology is a major
breakthrough in IC packaging concepts, using the die
as the package.
The SN74AUP1G79 device is fully specified for
partial-power-down applications using Ioff. The Ioff
circuitry disables the outputs when the device is
powered down. This inhibits current backflow into the
device which prevents damage to the device.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
SN74AUP1G79DBV SOT-23 (5)
2.90 mm × 1.60 mm
SN74AUP1G79DCK SC70 (5)
2.00 mm × 1.25 mm
SN74AUP1G79DRL SOT-5X3 (5)
1.60 mm × 1.20 mm
SN74AUP1G79DRY SON (6)
1.45 mm × 1.00 mm
SN74AUP1G79DSF SON (6)
1.00 mm × 1.00 mm
SN74AUP1G79DPW X2SON (5)
0.80 mm x 0.80 mm
SN74AUP1G79YFP DSBGA (6)
1.16 mm × 0.76 mm
SN74AUP1G79YZP DSBGA (5)
1.39 mm × 0.89 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Power Consumption and Performance
Switching Characteristics
at 25 MHz
3.5
3
2.5
2 Input
1.5
1
Output
0.5
0
−0.5
0
5
10 15 20 25 30 35 40 45
Time − ns
AUP1G08 data at CL = 15 pF
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.




etcTI

SN74AUP1G79 Datasheet Preview

SN74AUP1G79 Datasheet

Low-Power Single Positive-Edge-Triggered D-Type Flip-Flop

No Preview Available !

SN74AUP1G79
SCES592I – JULY 2004 – REVISED SEPTEMBER 2017
www.ti.com
Table of Contents
1 Features .................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions ......................... 3
6 Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information .................................................. 5
6.5 Electrical Characteristics: TA = 25°C ........................ 6
6.6 Electrical Characteristics: TA = –40°C to 85°C ......... 7
6.7 Timing Requirements ................................................ 8
6.8 Switching Characteristics: CL = 5 pF ........................ 9
6.9 Switching Characteristics: CL = 10 pF ...................... 9
6.10 Switching Characteristics: CL = 15 pF .................. 10
6.11 Switching Characteristics: CL = 30 pF .................. 11
6.12 Operating Characteristics...................................... 11
6.13 Typical Characteristics .......................................... 12
7 Parameter Measurement Information ................ 13
7.1 Propagation Delays, Setup and Hold Times, and
Pulse Width.............................................................. 13
7.2 Enable and Disable Times ...................................... 14
8 Detailed Description ............................................ 15
8.1 Overview ................................................................. 15
8.2 Functional Block Diagram ....................................... 15
8.3 Feature Description................................................. 15
8.4 Device Functional Modes........................................ 16
9 Applications, Implementation, and Layout ....... 17
9.1 Application Information............................................ 17
9.2 Typical Application .................................................. 17
10 Power Supply Recommendations ..................... 19
11 Layout................................................................... 19
11.1 Layout Guidelines ................................................. 19
11.2 Layout Example .................................................... 19
12 Device and Documentation Support ................. 20
12.1 Documentation Support ........................................ 20
12.2 Receiving Notification of Documentation Updates 20
12.3 Community Resources.......................................... 20
12.4 Trademarks ........................................................... 20
12.5 Electrostatic Discharge Caution ............................ 20
12.6 Glossary ................................................................ 20
13 Mechanical, Packaging, and Orderable
Information ........................................................... 20
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision H (April 2015) to Revision I
Page
• Added DPW (X2SON) package.............................................................................................................................................. 1
• Added Maximum junction temperature, TJ in Absolute Maximum Ratings ............................................................................ 4
• Changed values in the Thermal Information table to align with JEDEC standards. .............................................................. 5
• Added Balanced High-Drive CMOS Push-Pull Outputs, Standard CMOS Inputs, Clamp Diodes, Partial Power Down
(Ioff), Over-voltage Tolerant Inputs ........................................................................................................................................ 15
• Added Receiving Notification of Documentation Updates and Community Resources ....................................................... 20
Changes from Revision G (May 2010) to Revision H
Page
• Updated document to the new TI data sheet format .............................................................................................................. 1
• Removed Ordering Information table .................................................................................................................................... 1
• Added Device Information table ............................................................................................................................................ 1
• Added Typical Characteristics section.................................................................................................................................. 12
2
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Copyright © 2004–2017, Texas Instruments Incorporated
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Part Number SN74AUP1G79
Description Low-Power Single Positive-Edge-Triggered D-Type Flip-Flop
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