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SN74AUP1G97 Datasheet Preview

SN74AUP1G97 Datasheet

LOW-POWER CONFIGURABLE MULTIPLE-FUNCTION GATE

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SN74AUP1G97
www.ti.com
SCES505J – NOVEMBER 2003 – REVISED MAY 2010
LOW-POWER CONFIGURABLE MULTIPLE-FUNCTION GATE
Check for Samples: SN74AUP1G97
FEATURES
1
• Available in the Texas Instruments NanoStar™
Package
• Low Static-Power Consumption
(ICC = 0.9 mA Max)
• Low Dynamic-Power Consumption
(Cpd = 4.8 pF Typ at 3.3 V)
• Low Input Capacitance (CI = 1.5 pF Typ)
• Low Noise – Overshoot and Undershoot
<10% of VCC
• Ioff Supports Partial-Power-Down Mode
Operation
• Includes Schmitt-Trigger Inputs
• Wide Operating VCC Range of 0.8 V to 3.6 V
• Optimized for 3.3-V Operation
• 3.6-V I/O Tolerant to Support Mixed-Mode
Signal Operation
• tpd = 5.6 ns Max at 3.3 V
• Suitable for Point-to-Point Applications
• Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
• ESD Performance Tested Per JESD 22
– 2000-V Human-Body Model
(A114-B, Class II)
– 1000-V Charged-Device Model (C101)
DBV PACKAGE
(TOP VIEW)
B
1
6
C
GND
2
5
VCC
A
3
4
Y
DCK PACKAGE
(TOP VIEW)
B1
6
C
GND 2
5
VCC
A
3
4Y
DRL PACKAGE
(TOP VIEW)
B1
GND 2
A3
6C
5 VCC
4Y
DRY PACKAGE
(TOP VIEW)
DSF PACKAGE
(TOP VIEW)
B1
GND 2
A3
6C
V 5
CC
4Y
B1
GND 2
A3
6C
V 5
CC
4Y
See mechanical drawings for dimensions.
YFP PACKAGE
(TOP VIEW)
B C A1 1 6 A2
GND V B1 2 5 B2
CC
A Y C1 3 4 C2
YZP PACKAGE
(TOP VIEW)
B C A1 1 6 A2
GND V B1 2 5 B2
CC
A Y C1 3 4 C2
DESCRIPTION/ORDERING INFORMATION
The AUP family is TI's premier solution to the industry's low-power needs in battery-powered portable
applications. This family ensures a very low static- and dynamic-power consumption across the entire VCC range
of 0.8 V to 3.6 V, resulting in increased battery life (see Figure 1). This product also maintains excellent signal
integrity (see the very low undershoot and overshoot characteristics shown in Figure 2).
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2010, Texas Instruments Incorporated




etcTI

SN74AUP1G97 Datasheet Preview

SN74AUP1G97 Datasheet

LOW-POWER CONFIGURABLE MULTIPLE-FUNCTION GATE

No Preview Available !

SN74AUP1G97
SCES505J – NOVEMBER 2003 – REVISED MAY 2010
www.ti.com
Static-Power Consumption
(µA)
100%
80%
60%
3.3-V
Logic
40%
Dynamic-Power Consumption
(pF)
100%
80%
60%
40%
3.3-V
Logic
LVC
20%
20%
0%
AUP
0%
AUP
Single, dual, and triple gates
Figure 1. AUP – The Lowest-Power Family
Switching Characteristics
at 25 MHz
3.5
3
2.5
2 Input
Output
1.5
1
0.5
0
−0.5
0
5
10 15 20 25 30 35 40 45
Time − ns
AUP1G08 data at CL = 15 pF
Figure 2. Excellent Signal Integrity
The SN74AUP1G97 features configurable multiple functions. The output state is determined by eight patterns of
3-bit input. The user can choose the logic functions MUX, AND, OR, NAND, NOR, inverter, and noninverter. All
inputs can be connected to VCC or GND.
The device functions as an independent gate with Schmitt-trigger inputs, which allows for slow input transition
and better switching-noise immunity at the input.
NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
TA
–40°C to 85°C
ORDERING INFORMATION(1)
PACKAGE (2)
ORDERABLE PART NUMBER
NanoStar™ – WCSP (DSBGA)
0.23-mm Large Bump – YFP (Pb-free)
Reel of 3000 SN74AUP1G97YFPR
NanoStar™ – WCSP (DSBGA)
0.23-mm Large Bump – YZP (Pb-free)
Reel of 3000 SN74AUP1G97YZPR
QFN – DRY
Reel of 5000 SN74AUP1G97DRYR
uQFN – DSF
Reel of 5000 SN74AUP1G97DSFR
SOT (SOT-23) – DBV
Reel of 3000 SN74AUP1G97DBVR
SOT (SC-70) – DCK
Reel of 3000 SN74AUP1G97DCKR
SOT (SOT-553) – DRL
Reel of 4000 SN74AUP1G97DRLR
TOP-SIDE MARKING(3)
_ _ _HP_
_ _ _HP_
HP
HP
H97_
HP_
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(3) DBV/DCK/DRL: The actual top-side marking has one additional character that designates the wafer fab/assembly site.
YFP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the wafer fab/assembly site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, = Pb-free).
FUNCTION TABLE
INPUTS
C
B
A
OUTPUT
Y
L
L
L
L
L
L
H
L
L
H
L
H
L
H
H
H
H
L
L
L
H
L
H
H
H
H
L
L
H
H
H
H
2
Submit Documentation Feedback
Copyright © 2003–2010, Texas Instruments Incorporated
Product Folder Link(s): SN74AUP1G97


Part Number SN74AUP1G97
Description LOW-POWER CONFIGURABLE MULTIPLE-FUNCTION GATE
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